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SoCET Team

group photo of the soc team


Dr. Mark Johnson - advisor, taking picture
Dr. Matthew Swabey - advisor
Sutton Hathorn - advisor
Jacob Covey (MS) – Research Assistant

Current Students

John Martinuk (BS) – Physical Design, Polymorphic logic
Brian Graves (BS) - Physical Design, Polymorphic logic
Isaiah Grace (BS) - Physical Design, Polymorphic logic
Vadim Nikiforov (BS) – Sparsity optimized RISCV core
Chan Weng Yan (BS) – Sparsity optimized (SparCE) RISCV core
Vivekanandan (Vivek) Rajarajan (MS) Verification
Chandan Bothra (MS) - SoC integration
Radhika Jain (MS) - SoC Integration
Brian Helfrecht (BS) - Compiler for SparCE RISCV SoC
Nicholas Haythorn (BS) - Compiler for SparCE RISCV SoC
Alan Gregorian (BS) - Compiler for SparCE RISCV SoC
Karthik Maiya (BS) - JTAG controller
Cole Nelson (BS) - JTAG controller
Fred Owens (BS) - JTAG controller
Huy Minh Tran (BS) - RISCV software
Christopher Priebe (BS) - Wiki and Repository management
Luke Kok (BS) - Verification
Marco Garcia (BS)  - Verification
Cole Stecyk (BS) - Verification
Yupei Cao (BS) - Verification
Cesar Avalos (PhD) - SoC integration
Evelyn Ware (BS) - Analog (PLL) 
Matthew Olinde (BS) - Analog (PLL) 
Hyunoh Song (BS) - Analog (PLL) 
Jiahao Sun (BS) - PCB testbed
Yiming Ma (BS) - Verification
Zhewen Pan (BS) - Verification
James Zampa (BS) - ML code for SparCE RISCV
Tucker Swan (BS) - ML code for SparCE RISCV
Not in picture 
Jake Stevens (PhD) – Digital Design Lead
Manik Singhal (PhD) – Verification Lead
Xianmeng (Simon) Zhang (BS) – JTAG controller
Atif Nayaz (BS) - Compiler for SparCE RISCV SoC


Over 100 since formation of team in 2012. List under construction. Alumni who see this and want to be listed are encouraged to contact Dr. Johnson.