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ECE67000 - Modeling and Optimization of High-Performance Interconnects

Fall 2015

Days/Time: TTh / TBA
Credit Hours: 3

Learning Objective:
1. Understand how on-chip interconnects affect the performance of very large scale integration (VLSI) circuits and systems. 2. Understand different models of on-chip interconnects. 3. Learn different algorithms/approaches for optimizing performance on-chip interconnects. 4. Learn algorithms for the synthesis of clock distribution networks.

Description:
There are two major components in a VLSI circuit/system: devices that perform the computation and interconnects that allow devices to communicate with each other. While the scaling of silicon technologies makes devices switch faster, it leads to relatively slower interconnects. This course deals with many aspects of on-chip interconnects, helping circuit designers understand better the algorithms or techniques that state-of-the-art computer-aided-design tools use to deal with these interconnects. The modeling of interconnects will start with the extraction of resistive-inductive-capacitive parasitics of on-chip interconnects. Reduced-order modeling of such interconnect networks will be studied. Techniques to reduce the simulation times of large-scale on-chip interconnects will also be covered. The synthesis of interconnects will examine a common technique used to reduce interconnect delay, namely repeater insertion. In particular, Repeater insertion for tree structures will be displayed extensively. Some of these modeling and synthesis techniques will be put into practice in the form of clock network synthesis. Clock distribution networks are typically one of the largest on-chip interconnects.

Topics Covered:
1. Modeling of interconnects: Extraction of parasitics (resistance, capacitance, and inductance) 2. Analysis of interconnects: Reduced order modeling and simulation 3. Synthesis and optimization of interconnects: buffer insertion, clock network optimization.

Prerequisites:
ECE 559 (or equivalent), or consent of instructor

Applied/Theory: 70/30

Web Address:
http://www.itap.purdue.edu/learning/tools/blackboard/

Web Content:
Syllabus, Grades, Lecture Notes, Homework Assignments and Message Board.

Homework:
About 5 (written) homework assignments. Solutions to these assignments are discussed in class. Homework will be submitted via Blackboard.

Projects:
Term projects investigating clock network synthesis are assigned. These projects will require the writing of C programs and running ng-spice on Linux workstations/PCs

Exams:
1 Final exam

Textbooks:
Reference: Handbook of Algorithms for Physical Design Automation, ed. Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, CRC Press, 2009. Reference: Electronic Design Automation: Synthesis, Verification, and Test, ed. Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng, Elsevier Inc., 2009

Computer Requirements:
ProEd Minimum Computer Requirements. The students will have to write C programs and run ng-spice on Linux workstations/PCs.

ProEd Minimum Requirements: view

Tuition & Fees: view

Other Requirements:
None.

Cheng-kok Koh
Phone
765-496-3683
Email
chengkok@purdue.edu
Office
Purdue University
Electrical Engineering Building
465 Northwestern Ave
West Lafayette, IN 47907-2035
Instructor HomePage