Publications by Research Area

I. Purdue Exploratory Technology Evaluator (PETE)

Descritpion: Using PETE one can evaluate any MOSFET like devices or any New Devices in terms of performance on Benchmark circuits. The input to the tool can be in terms of typical MOSFET parameters or in terms of IV and CV tables. The Benchmark circuits include minimum sized inverter, nand chain, norchain, 8bit Full Adder, Ring Oscillator and Cascaded inverters driving a big load capacitance. Further, one can perform DC simulations on inverters and obtain voltage transfer characteristics (VTCs) and noise margin/ gain from the VTC.

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II. SRAM and FinFET/SingleGate Fully Depleted SOI Papers



III. Publications in FinFET Research


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IV. Publications on Process Variations and NBTI impact in Memory Designs


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V. Designing circuits beyond traditional Silicon

Journal Papers
2007
1. A. Raychowdhury and K. Roy, "Carbon Nanotube Electronics: Design of High Performance and Low Power Digital Circuits," IEEE Transactions on Circuits and Systems  I, special issue on Nanotechnology, to appear
2006
1. A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, Analysis of Carbon Nanotube Field Effect Transistors for High Performance Digital Logic  Modeling and DC Simulations, IEEE Transactions on Electron Devices, Vol. 53, Issue 11, November 2006, pp: 27112717.
2. A. Keshavarzi, A. Raychowdhury, J. Kurtin, K. Roy, and V. De, Analysis of Carbon Nanotube Field Effect Transistors for High Performance Digital Logic Transient Analysis, Parasitics and Scalability, IEEE Transactions on Electron Devices, Vol. 53, Issue 11, November 2006, pp: 27182726.
3. A. Raychowdhury and K. Roy, Modeling of Metallic Carbon Nanotube Interconnects for Circuit Simulations and a Comparison with Cu Interconnects for Scaled Technologies, IEEE Transactions on Computer Aided Design, Vol. 25, Issue 1, January 2006, pp: 5865.
4. A. Raychowdhury and K. Roy, Carbon nanotube based voltagemode multiplevalued logic design, IEEE Transactions on Nanotechnology, Vol. 4, Issue 2, March 2005, pp: 168  179.
2005
5. M. Hwang, A. Raychowdhury, and K. Roy, Energy Recovery Techniques to Reduce Onchip Power Density in Molecular NanoTechnologies, IEEE Transactions on Circuits and Systems I, Vol. 52, no. 8, August 2005, pp: 15801589.
2004
6. A. Raychowdhury, S. Mukhopadhyay and K. Roy, A Circuit Compatible Model of Ballistic Carbon Nanotube Field Effect Transistors, IEEE Transactions on Computer Aided Design, Vol. 23, no. 10, October 2004, pp: 14111420.
Conference Papers
2006:
1. A. Raychowdhury, X. Fong, Q. Chen, and K. Roy, Analysis of Super Cutoff Transistors for Ultralow Power Digital Logic Circuits, Proc. of the International Symposium of Low Power Electronic Design (ISLPED), October 2006, pp: 16. (Best paper Award)
2. M. Budnik, A. Raychowdhury, Aditya Bansal and K. Roy, CNCAP: Design of a high density Carbon Nanotube Capacitor Structure, Proc. of the Design Automation Conference (DAC), July 2006.
3. A. Raychowdhury, J. Kim, D. Peroulis, and K. Roy, Integrated MEMS Switches for Leakage Control of Battery Operated Systems, Proc. of the Custom Integrated Circuit Conference (CICC), September 2006.
4. A. Raychowdhury, and K. Roy, Using Super Cutoff Carbon Nanotube Sleep Transistors in Silicon Based Low Power Digital Circuits, Proc. of the IEEE Nano, Cincinnati, September 2006.
5. A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, Optimal Spacing of Carbon Nanotubes in a CNFET Array for Highest Circuit Performance, Proc. of the Device Research Conference (DRC), June 2006.
6. A. Raychowdhury, and K. Roy, Carbon Nanotubes for Digital Circuit Design, Proc. of the Government Microcircuit Applications and Critical Technology Conference, GomacTech, March 2005. (Invited)
7. M. Budnik, A. Raychowdhury, K. Roy, Power Delivery for Nanoscale Processors with Single Wall Carbon Nanotube Interconnects, Proc. of the IEEE Nano, Cincinnati, September 2006.
2005
8. A. Raychowdhury, Jing Guo, K. Roy, and Mark Lundstrom, Design of a novel threevalued static memory using Schottky barrier carbon nanotube FETs, Proc. of the Fourth IEEE Nano Conference, Munich, July 2005, pp: 507 510.
2004
9. A. Raychowdhury and K. Roy, Carbon Nanotubes as Interconnects of the Future: A Circuit Perspective, Proc. of the Advanced Metallization Conference, San Diego, October 2004. (Invited)
10. A. Raychowdhury and K. Roy, Circuit Modeling of Carbon Nanotube Interconnects and their Performance Estimation in VLSI Design, Proc. of the International Workshop on Computational Electronics (IWCE), West Lafayette, October 2004.
11. A. Raychowdhury and K. Roy, A Circuit Model for Carbon Nanotube Interconnects: Comparative Study with Cu Interconnects for Scaled Technologies, Proc. of the International Conference on Computer Aided Design (ICCAD), San Jose, November 2004, pp: 237240.
12. A. Raychowdhury and K. Roy, Modeling and Analysis of Carbon Nanotube Interconnects for High Speed VLSI Design, Proc. of the Fourth IEEE Nano Conference, Munich, August 2004, WEP37.
13. A. Raychowdhury, Jing Guo, K. Roy, and Mark Lundstrom, Choice of FlatBand Voltage, VDD and Diameter of Ambipolar SchottkyBarrier Carbon Nanotube Transistors in Digital Circuit Design, Proc. of the Fourth IEEE Nano Conference, Munich, August 2004, TH221.
14. A. Raychowdhury and K. Roy, A Novel MultipleValued Logic Design Using Ballistic Carbon nanotube FETs, Proc. of the 34th International Symposium on MultipleValued Logic (ISMVL), Toronto, May 2004, pp: 1419.
2003
15. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation, Proc. of the International Conference on Computer Aided Design (ICCAD), San Jose, November 2003, pp: 465469.
16. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Circuitcompatible modeling of carbon nanotube FETs in the ballistic limit of performance, Proc. of the Third IEEENano Conference, San Francisco, August 2003, pp: 343346. (Best Paper Award)
17. A. Raychowdhury and K. Roy, Performance Estimation in Molecular Crossbar Architecture Considering Capacitive and Inductive Coupling Between Interconnects", Proc. of the Third IEEENano Conference, San Francisco, August 2003, pp: 445448.

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VI. High Performance and Low Power Flexible Electronics

Journal Publications:
2007
1. Jing Li, A. Bansal and K. Roy; PolySi Thin Film Transistors: An efficient and low cost option for digital subthreshold operation, accepted for publication in IEEE Transactions on Electron Devices (TED), 2007.
Conference Publications:
2007
1. Jing Li, K. Kang, A. Bansal and K. Roy, High performance and low power electronics on flexible substrates, accept by Design Automation Conference (DAC), 2007.
2. Jing Li, K. Kang and K. Roy, Novel variationaware circuit design of scaled LTPS TFT for ultra low power, lowcost applications, accept by Intl. Conf. on IC Design & Technology (ICICDT), 2007
2006
1. Jing Li, A. Bansal and K. Roy; Exploring low temperature PolySi for low cost and low power submicron digital operation, Device Research Conference (DRC), 2006.

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VII. Low Power Electronics

Journal Publications:
2007
1. N. Banerjee, A Raychowdhury, K. Roy, S. Bhunia, and H. Mahmoodi, Low Power Datapath Synthesis Using Supply Gating Based Operand Isolation Techniques, IEEE Transactions on VLSI Systems (TVLSI), to appear
2006
4. N. Banerjee, A Raychowdhury, K. Roy, S. Bhunia, and H. Mahmoodi, Novel LowOverhead Operand Isolation Techniques for LowPower Datapath Synthesis, IEEE Transactions on VLSI Systems, September 2006, pp. 10341039. (no 118)
2005
4. S. Bhunia, A. Datta, N. Banerjee, and K. Roy, GAARP: A PowerAware GALS Architecture for RealTime AlgorithmSpecific Tasks, IEEE Transactions on Computer, special issue on lowpower design, June 2005, pp. 752766. (no. 99)
2002
2. A. Solomatnikov, D. Somasekhar, N. Sirisantana, and K. Roy, Skewed CMOS: Noise Tolerant High Performance and Low Power Static Circuit Family, IEEE Transactions on VLSI Systems, pp. 469476, August 2002.
Conference Publications
2006
10. N. Banerjee, H. Mahmoodi, S. Bhunia, and K. Roy, Low Power Synthesis of Dynamic Logic Circuits using FineGrained Clock Gating, IEEE Design and Test in Europe (DATE), March 2006. (no 411)
2005
12. N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy, Novel LowOverhead Operand Isolation Techniques for LowPower Datapath Synthesis, IEEE International Conference on Computer Design (ICCD), October 2005.(no 396)
13. S. Bhunia, H. Mahmoodi, N. Banerjee, Q. Chen, and K. Roy, A Novel Synthesis Approach for Active Leakage Power Reduction Using Supply Gating, IEEE/ACM Design Automation Conference (DAC), June 2005.(no 384)
14. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, Statistical Modeling of Pipeline Delay and Design of Pipeline Under Process Variation to Enhance Yield in Sub100nm Technologies, IEEE Design and Test in Europe (DATE), pp. 926931, 2005. (no 373)
15. A. Datta, S. Bhunia, N. Banerjee, and K. Roy, A PowerAware GALS Architecture for RealTime AlgorithmSpecific Tasks, IEEE International Symposium on Quality Electronic Design, pp.358363, 2005. (no 365)
2003
10. Y. Chen, K. Roy, and CK. Koh, Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance ClockGated Microprocessor, IEEE International Symposium on LowPower Electronics and Design, pp. 229234, August 2003. (no 316)
11. A. Agarwal and K. Roy, A Noise Tolerant Cache Design to Reduce Gate and Subthreshold Leakage in the Nanometer Regime, IEEE International Symposium on LowPower Electronics and Design, pp. 1821, August 2003. (no 314)
12. W. Jeong and K. Roy, Robust HighPerformance LowPower Carry Select Adder, IEEE AsiaSouthPacific Design Automation Conference, January 2003. (no 204)
2001
5. J. Kim and K. Roy, A Leakage Tolerant High Fanin Dynamic Circuit Design Technique, European Solid State Circuits Conference, September 2001.(no 267)
6. N. Sirisantana, A. Caoa, S. Davidson, C. Koh, and K. Roy, Selectively Clocked Skewed Logic (SCSL): A Robust LowPower Logic Style for HighPerformance Applications, ACM/IEEE International Symposium on Low Power Electronics and Design, August 2001, pp. 267270. (no 265)

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VIII. Low Power, Variation Aware DSP system design

Selected Journal Publications:
2008
1) J.H. Choi, N. Banerjee, and Kaushik Roy, VariationAware LowPower Synthesis Methodology for FixedPoint FIR Filters,IEEE Transactions on COMPUTERAIDED DESIGN of Integrated Circuits and Systems(to appear)
Selected Conference Publications:
2007
1) Process Variation Tolerant Low Power DCT Architecture, IEEE Design, Automation and Test in Europe (DATE), April 2007
2) An Optimal Algorithm for Low Power Multiplierless FIR Filter Design Using Chebychev Criterion, ICASSP 2007

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IX. Memory Technology and Design

Journal Publications:
2007
1. S. Mukhopadhyay, K. Kim, K. Kang, H. MahmoodiMeimand, A. Datta, Dongkyu Park and K. Roy, "Design of a Process Variation Tolerant SelfRepairing SRAM for Yield Enhancement in Nanoscaled CMOS," accepted for publication in IEEE Journal of Solid State Circuits
2. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, Reduction of Parametric Failures in Sub100nm SRAM Array using Body Bias, accepted for publication in IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems
3. A. Bansal, S. Mukhopadhyay, and K. Roy, Device Optimization Technique for Robust and LowPower FinFET SRAMs, accepted for publication in IEEE Transactions on Electron Devices.
2006
1. C. H. Kim, J. Kim, I. Chang, and K. Roy, "PVT Aware Leakage Reduction for OnDie Caches Using SelfDecay Scheme", IEEE Journal of SolidState Circuits, Vol. 41, Issue 1, pp. 170178, Jan. 2006
2. S. Mukhopadhyay, Hamid Mahmoodi, and K. Roy, Design of High Performance Sense Amplifier Using Independent Gate Control in Fully Depleted DoubleGate MOSFET, IEEE Transaction on VLSI Systems (TVLSI), March, 2006.
2005
1. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in NanoScaled CMOS, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems , Dec. 2005.
2. A. Agrawal, B. Paul, H. Mahmoodi, A. Datta, and K. Roy, "A ProcessTolerant Cache Architecture for Improved Yield in Nanoscale Technologies," IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 1, pp. 2738, Jan. 2005
3. A. Agarwal, B. Paul, S. Mukhopadhyay, and K. Roy, Process Variation in Embedded Memories: Failure Analysis and Process Tolerant Architecture, IEEE Journal of Solid State Circuits , Sept. 2005
4. C. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, A Forward BodyBiased LowLeakage SRAM Cache: Device and Architecture Considerations, IEEE Transactions on VLSI Systems, March 2005.
Conference Publications:
2008
1. N. N. Mojumder, S. Mukhopadhyay, J. Kim, C. T. Chuang, K. Roy, "Design and Analysis of a SelfRepairing SRAM with OnChip Monitor and Compensation Circuitry," IEEE VLSI Test Symposium 2008, April 2008
2007
1. J. P. Kulkarni and K. Roy A High Performance Scalable Multiplexed Keeper Technique 2007 International Symposium on Quality Electronics Design (ISQED), pp. 545549, March 2007
2006
1. S. Gangwal, S. Mukhopadhyay and K. Roy, Optimization of Surfaceorientation for high performance, low power and robust FinFET SRAM, CICC 2006.
2. A. Goel, S. Bhunia, H. Mahmoodi and K. Roy, LowOverhead Design of SoftErrorTolerant Scan FlipFlops with EnhancedScan Capability, Asia South Pacific Design Automation Conference 2006.
3. S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, SelfRepairing SRAM for Reducing Parametric Failures in Nanoscaled Memory, Symp. on VLSI Circuits, 2006.
4. S. Mukhopadhyay, A. Agarwal, Q. Chen, and K. Roy, SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design (INVITED), IEEE Custom Integrated Circuit Conference, 2006.
5. S. Mukhopadhyay, S. Ghosh, K. Kim, and K. Roy, LowPower and Process Variation Tolerant Memories in sub90nm Technologies (INVITED), IEEE Intl. SystemOnChip Conf., 2006.
2005
1. A. Bansal, S. Mukhopadhyay and K. Roy, Modeling and Optimization Approach to Robust and LowPower FinFET SRAM Design in Nanoscale Era. Proc. of the IEEE Custom Integrated Circuits Conference (CICC), 2005, pp. 835838.
2. I. J. Chang, K. Kang, S. Mukhopadhyay, C.H. Kim, K. Roy, Fast and Accurate Estimation of NanoScaled SRAM Read Failure Probability using Critical Point Sampling, Custom Intergrated Circuit Conference (CICC), Sep. 2005
3. C. H. Kim, J. Kim, I. Chang and K. Roy, "PVTAware Leakage Reduction for Ondie Caches with Improved Read Stability", International SolidState Circuits Conference (ISSCC), Feb. 2005
4. K. Kim, C. H. Kim, and K. Roy, "TFTLCD Application Specific Low Power SRAM Using ChargeRecycling Technique", International Symposium on Quality Electronics Design (ISQED), Mar. 2005
5. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Design of High Performance Sense Amplifier Using Independent Gate Control in Fully Depleted DoubleGate MOSFET," Intl. Symp. on Quality Electronic Design (ISQED), 2005.
6. S. Mukhopadhyay, K. Kang, H. Mahmoodi, and K. Roy, Reliable and SelfRepairing SRAM in Nanoscale Technologies using Leakage and Delay Monitoring, Intl. Test Conf. (ITC), 2005.
7. S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, and K. Roy, Leakage current based stabilization scheme for robust senseamplifier design for yield enhancement in nanoscale SRAM, Asian Test Symp. (ATS), 2005.
2004
1. H. Ananthan, A. Bansal and K. Roy, FinFET SRAM  Device and Circuit Design Considerations. Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2004, pp. 511516.
2. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling and Estimation of Failure Probability due to Parameter Variations in Nanoscale SRAMs for Yield Enhancement," Symp. on VLSI Circuits, 2004.
3. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Statistical Design and Optimization of SRAM Cell for Yield Enhancement," Intl. Conf. on Computer Aided Design, 2004.
2003
1. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A Forward BodyBiased LowLeakage SRAM: Device and Architecture Considerations", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2003
2002
1. C. H. Kim, K. Roy, "Dynamic Vth SRAM : A Leakage Tolerant Cache Memory for Low Voltage Microprocessors ", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2002
2. H. Mahmoodi and K. Roy, Selfprecharging flipflop (SPFF): a new level converting flipflop, European SolidState Circuits Conference, pp. 407410, Sep. 2002

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X. Process Variations and Error Resilience

Journal Publications:
2008
1. A. Datta, S. Bhunia, J.H. Choi, S. Mukhopadhyay, and K. Roy, Profit Aware Circuit Design under Process Variations Considering Speed Binning IEEE TVLSI, July 2008
2007
1. S. Ghosh, S. Bhunia, and K. Roy, CRISTA: A New Paradigm for Lowpower, VariationTolerant and Adaptive Circuit Synthesis Using Critical Path Isolation, IEEE Transactions on ComputerAided Design of ICs, to appear. (no. 134)
2. Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, and Muhammad A. Alam, "Impact of Negative Bias Temperature Instability in NanoScale SRAM Array: Modeling and Analysis," IEEE Transactions on Computer Aided Design of ICs, to appear.
3. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher and Kaushik Roy, "DeviceAware YieldCentric DualVt Design under Parametric Variations in NanoScale Technologies," IEEE Transactions on VLSI, to appear
4. Saibal Mukhopadhyay, Keejong Kim, Kunhyuk Kang, Hamid Mahmoodi, Animesh Datta, Dongkyu Park and Kaushik Roy, "Design of a Process Variation Tolerant SelfRepairing SRAM for Yield Enhancement in Nanoscaled CMOS," accepted for publication in IEEE Journal of Solid State Circuits.
5. B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, ``Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits,'' IEEE Transactions on ComputerAided Design of Integrated Circuits, April 2007, pp. 743751. (no 125)
2006
1. A.Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, ``Modeling of Pipeline Delay and Statistical Design of Pipeline under Process Variations,'' IEEE Transactions on ComputerAided Design of Integrated Circuits}, November 2006, pp. 24272436. (no 123)
2. K. Kang, B. Paul, and K. Roy, Statistical Timing Analysis using Levelized Covariance Propagation Considering Systematic and Random Variations of Process Parameters, ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 4, October 2006, pp. 848879. (no 122)
3. C.H. Kim, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, A Process variation Compensating Technique With an OnDie Leakage Current Sensor for Nanometer Scale Dynamic Circuits, IEEE Journal of SolidState Circuits, June 2006, pp. 646649. (no 115)
2005
1. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Estimation of Delay Variations due To RandomDopant Fluctuations in Nanoscale CMOS Circuits, IEEE Journal of SolidState Circuits, September 2005, pp. 17871796. (no 103)
2. B. Paul, K. Kang, H. Kufluoglu, A. Alam, and K. Roy, Impact of NBTI on the Temporal Performance Degradation of Digital Circuits, IEEE Electron Device Letters, August 2005, pp. 560562. (no 101)
3. A. Agarwal, B. Paul, H. Mohammadi, A. Datta, and K. Roy, A Process Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies, IEEE Transactions on VLSI Systems, January 2005, pp. 2738. 2005 IEEE Circuits and Systems Society VLSI Transactions Best Paper Award. (no. 85)
2002
1. A. Keshavarzi, K. Roy, J. Tschantz, S. Narendra, A. Daasch, C. Hawkins, and V. De, Impact of Leakage and Process Variation on CurrentBased Testing for Future Scaled CMOS Circuits, IEEE Design and Test, SeptemberOctober 2002, pp. 3643. (no 66)
Conference Publications:
2007
1. S. Ghosh, S. Bhunia, and K. Roy,A Fault Tolerant Technique for Improved Yield in Nanometer Technologies by Adaptive Clock Stretching, International OnLine Test Symposium, 2007. (no 444)
2. M. Hwang, K. Kim, A. Raychowdhury, and K. Roy, An 85mV 40nW Process Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology, IEEE VLSI Circuit Symposium, June 2007. (no 442)
3. Kunhyuk Kang, Keejong Kim, and Kaushik Roy, "Variation Resilient LowPower Circuit Design Methodology using OnChip Phase Locked Loop," accepted for publication in Design Automation Conference, June 2007. (no 439)
4. Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad A. Alam, and Kaushik Roy, "Characterization and Estimation of Circuit Reliability Degradation under NBTI using OnLine IDDQ Measurement," accepted for publication in Design Automation Conference, June 2007, nominated for bestpaper award.
5. Kunhyuk Kang, Muhammad A. Alam, and Kaushik Roy, "Estimation of NBTI Degradation Using OnChip IDDQ Measurement," IEEE International Reliability Physics Symposium, April 2007, pp. 1016.
6. M. Hwang, T. Cakici, A. Raychowdhury, and K. Roy, Process Variation Tolerant Betaratio Modulation with Ultra Dynamic Voltage Scaling, Design Automation and Test in Europe, April 2007, nominated for bestpaper award. (no 436)
7. N. Banerjee, G. Karakonstantis, and K. Roy, Process Variation Tolerant LowPower DCT Architecture, Design Automation and Test in Europe, April 2007. (no 435)
8. S. Ghosh, S. Bhunia, and K. Roy, LowOverhead Circuit Synthesis for Temperature Adaptation using Dynamic Voltage Scheduling, Design Automation and Test in Europe, April 2007. (no 434)
9. S. Mukhopadhyay, K. Kim, K. Jenkins, C.T. Chuang, and K. Roy,Statistical Characterization and OnChip Measurement Methods for Local Random Variability Using SenseAmplifierBased Test Structure, 2007 International SolidState Circuits Conference (ISSCC), February 2007., pp 400402 (no 431)
2006
1. S. Ghosh, S. Bhunia, and K. Roy, A New Paradigm for Lowpower, VariationTolerant and Adaptive Circuit Synthesis Using Critical Path Isolation, IEEE International Conference on ComputerAided Design of ICs , 2006. (no 429)
2. Kunhyuk Kang, Haldun Kufluoglu, Muhammad A. Alam, and Kaushik Roy, "Efficient TransistorLevel Sizing Technique under Temporal Performance Degradation due to NBTI," IEEE International Conference on Computer Design, October 2006, pp. 216221.
3. S. Mukhopadhyay, A. Agarwal, Q. Chen and K. Roy, SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design, IEEE Custom Integrated Circuits Conference, September 2006, Invited Paper. (no 426)
4. S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, SelfRepairing SRAM for Reducing Parametric Failures in NanoscaledMemory, IEEE 2006 Symposium on VLSI Circuits, June 2006. (no 416)
5. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy,Temporal Performance Degradation Under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits, IEEE Design and Test in Europe (DATE), March 2006.
6. Kunhyuk Kang, Muhammad A. Alam, and Kaushik Roy, "Analysis and Design of NanoScale Digital CMOS Circuits under Spatial and Temporal Reliability Degradation," SRC Student Symposium, 2006.
7. A. Goel, S. Bhunia, H. Mahmoodi, and K. Roy, A LowOverhead Design of SoftErrorTolerant Scan FlipFlop with EnhancedScan Capability, Asia and South Pacific Design Automation Conference, pp. 665670, January 2006. (no 407)
8. H. Li, Y. Chen, K. Roy, and C.K. Koh, SAVS: A SelfAdaptive Variable Supply Voltage Technique for ProcessTolerant and PowerEfficient MultiIssue Superscalar Processor Design, Asia and South Pacific Design Automation Conference, pp. 158163, January 2006 (no. 406)
9. A. Datta, S. Bhunia, S Mukhopadhyay, J. Choi, and K. Roy, Speed Binning Aware Design Methodology to Improve Profit under Parameter Variation, Asia and South Pacific Design Automation Conference, January 2006, pp. 712 717, nominated for best paper award (no 405)
2005
1. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, A Statistical Approach to AreaConstrained Yield Enhancement for Pipelined Circuits under Parameter Variations, 14th Asian Test Symposium, December 2005. (no 401)
2. A. Agarwal, K. Kang, and K. Roy, Accurate Estimation and Modeling of Total Chip Leakage Considering Inter and IntraDie Process Variations, IEEE International Conference on ComputerAided Design (ICCAD), November 2005. (no 400)
3. P. Ndai, A. Agarwal, Q. Chen, and K. Roy, A SoftError Monitor Using Switching Current Detection, IEEE International Conference on Computer Design (ICCD), October 2005. (no 394)
4. Y. Chen, H. Li, K. Roy, and C.K. Koh, Cascaded CarrySelect Adder (C2SA): A New Structure for LowPower CSA Design, ACM/IEEE International Symposium on LowPower Electronics and Design, August 2005, pp. 115118. (no 388)
5. S. Hsu, A. Agarwal, K. Roy, R. Krishnamurthy, and S. Borkar, An 8.3 GHz Dual Supply/Threshold Optimized 32b Integer ALURegister File Loop in 90nm CMOS, ACM/IEEE International Symposium on LowPower Electronics and Design, August 2005, pp. 103106. (no 387)
6. A. Agarwal, K. Kang, S. Bhunia, J. Gallagher, and K. Roy, Effectiveness of DualVt Designs in NanoScale Technologies under Process Variations, ACM/IEEE International Symposium on LowPower Electronics and Design, August 2005, pp. 1419. (no 386)
7. M. Alam, H. Kufluoglu, B. Paul, K. Kang, and K. Roy, On Reliable Circuits and Systems: How Reliability Considerations are Reshaping Oxide Scaling, Device Geometry, and VLSI Algorithm, 2005 IEEE International Conference on Integrated Circuit and Technology, May 2005, pp. 117122 (no 383)
8. C. Kim, K. Roy, S. Hsu, R. Krishnamurthy and S. Borkar, An OnDie Leakage Current Sensor for Measuring Process Variation in Sub90nm Generations, 2005 IEEE International Conference on Integrated Circuit and Technology, May 2005, pp. 221222. ( no 382)
9. A. Datta, S. Mukhopadhyay, S. Bhunia, and K. Roy, Reliability Analysis and Yield Prediction of High Performance Pipelined Circuit with respect to Delay Failures in sub100nm Technology,IEEE International Symposium on OnLine Testing, 2005. ( no 379)
10. K. Kang, B. Paul, and K. Roy, Statistical Timing Analysis using Levelized Covariance Propagation, IEEE Design and Test in Europe (DATE), pp. 764769, 2005. (no 371)
11. C.H. Kim, J. Kim, I, Kim, and K. Roy, A Process and Temperature Variation Aware Leakage Reduction Technique with Improved Stability for OnDie Caches, IEEE International SolidState Circuits Conference, pp. 482483, February 2005. (no 363)
2004
1. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Estimation of Delay Variations Due to Random Dopant Fluctuations in NanoScaled CMOS Circuits, IEEE Custom Integrated Circuits Conference, Oct. 2004 ( no 349)
2. A. Agarwal, B. Paul, and K. Roy, Process Variation in NanoScale Memories: Failure Analysis and ProcessTolerant Architecture, IEEE Custom Integrated Circuits Conference, October 2004. (no 348)
3. S. Choi, B. Paul, and K. Roy, Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology, IEEE/ACM Design Automation Conference, pp. 454459, June 2004. (no 343)
4. S. Mukhopadhyay, H. MahmoodiMeimand, and K. Roy, Modeling and Estimation of Failure Probability due to Parameter Variations in NanoScaled SRAMs for Yield Enhancement, IEEE 2004 Symposium on VLSI Circuits, pp. 6467, June 2004. (no 341)
5. C. Kim, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, An OnDie CMOS Leakage Sensor for Measuring Process Variation in Sub90nm Generation, IEEE 2004 Symposium on VLSI Circuits, pp. 250251, June 2004. (no 340)
6. A. Agarwal, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, 90nm 6.5GHz 128X64 4Read 4Write Ported Parameter Variation Tolerant Register File, IEEE 2004 Symposium on VLSI Circuits, pp. 386387, June 2004. (no 339)
2003
1. H. Li, C. Cher, T. Vijaykumar, and K. Roy, VSV: L2MissDriven Variable Supply Voltage Scaling for LowPower, IEEE Micro, pp. 1928, December 2003.( no 327)
2. H. Suzuki, W. Jeong, and K. Roy, Low Power Adder with Adaptive Supply Voltage, IEEE International Conference on Computer Design, pp. 103106, 2003. (no 322)
3. S. Mukhopadhyay and K. Roy, Modeling and Estimation of Total Leakage Current in NanoScaled CMOS Devices Considering the Effect of Process Variation, IEEE International Symposium on LowPower Electronics and Design, pp. 172175, August 2003. (no 315)
4. C. Neau and K. Roy, Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations, IEEE International Symposium on LowPower Electronics and Design, pp. 116121, August 2003. (no 312)
5. C. H. Kim, K. Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, and S. Borkar, A Process Varia tion Compensating Technique for Sub90nm Dynamic Circuits, IEEE 2003 Symposium on VLSI Circuits, pp. 205206, June 2003 (no 308)
6. Y. Im and K. Roy, A LogicAware Layout Methodology to Enhance the Noise Immunity of Domino Circuits, IEEE International Symposium on Circuits and Systems, May 2003. (no 305)
7. N. Sirisantana and K. Roy, Selectively Clocked CMOS Logic Style for LowPower NoiseImmune Operations in Scaled Technologies, IEEE Design and Test in Europe (DATE), 11601161, March 2003. (no 300)
8. S. Choi and K. Roy, A New Crosstalk Noise Model for DOMINO Logic Circuits, IEEE Design and Test in Europe (DATE), pp. 11121113, March 2003. (no 299)
9. Y. Im and K. Roy, LALM: A LogicAware Layout Methodology to Enhance the Noise Immunity of Domino Circuits, IEEE International Symposium on VLSI, pp. 4552, 2003.(no 295)
2002
1. S. Choi, F. Dartu, and K. Roy, Timed Pattern Generation for NoiseonDelay Calculation, ACM/IEEE Design Automation Conference, June 2002, pp. 870873. (no 284)
2. S. Choi and K. Roy, Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits, IEEE International Workshop on Electronic Design, Test, and Applications, Christchurch, New Zealand, January 2002, pp. 365369.(no 274)
3. S. Zhao, K. Roy, and C.K. Koh,, Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement, AsiaSouth Pacific Design Automation Conference/ VLSI Conference, 2002, pp. 489495 (no 273)
4. S.H. Choi, B. Paul, and K. Roy, Dynamic Noise Analysis with Capacitive and Inductive Coupling in PrechargeEvaluate Circuits, AsiaSouth Pacific Design Automation Conference/ VLSI Conference, 2002, pp. 6570. (no 272)
2001
1. Y. Im and K. Roy, CASh: A Novel Clock As Shield Design Methodology for Noise Immune PrechargeEvaluate Logic, IEEE International Conference on ComputerAided Design, November 2001. (no 270)
2. B. Paul, S.H. Choi, Y. Im, and K. Roy, Design Verification and Robust Design Technique for CrossTalk Faults, Asian Test Symposium, November 2001, pp. 449454. (no 269)
3. S.H. Choi, D. Somasekhar, and K. Roy, Dynamic Noise Model and Its Application to High Speed Circuit Design, IEEE MixedSignal Test Workshop, Lake Lanier, Georgia, June 2001. (no 265)
4. S. Zhao, K. Roy, and C.K. Koh, Decoupling Capacitance Allocation for Power Supply Noise Suppression, Internation Symposium on Physical Design, April 2001. (no 258)
2000
1. A. Solomatnikov, D. Somasekhar, and K. Roy, Skewed CMOS: NoiseImmune HighPerformance LowPower Static Circuit Family, European SolidState Circuits Conference, pp 424427, Sep. 2000.( no 247)
2. S. Zhao, K. Roy, and C. Koh, Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Submicron CMOS Circuits, IEEE International Conference on Computer Design, 2000, pp. 6572. (no 245)
3. D. Somasekhar, S. Choi, K. Roy, Y. Ye, and V. De, Dynamic Noise Immunity in Precharge Evaluate Circuits, ACM/IEEE Design Automation Conf., 2000, pp. 243246. (no 240)
4. S. Zhao and K. Roy, Estimation of Worst Case Switching Noise on Power Supply Lines in Deep Submicron CMOS Circuits, International Conference on VLSI Design, Jan. 2000, pp. 168173. (no 234)

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Conference Papers:
2008
1. S. Ghosh, J.H. Choi, P. Ndai and K. Roy, "O2C: Occasional TwoCycle Operations for Dynamic Thermal Management in High Performance InOrder Microprocessors," Proc. of the International Symposium of Low Power Electronic Design (ISLPED), August 2008.
Journal Papers:
2007
1. K. Kang, H. Kufluoglu, K. Roy, and M. A. Alam, "Impact of Negative Bias Temperature Instability in NanoScale SRAM Array: Modeling and Analysis," accepted for publication in IEEE Transactions on Computer Aided Design.
2. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy, "Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits," IEEE Transactions on Computer Aided Design, vol. 26, no. 4, April 2007, pp. 743751.
2005
1. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy, "Impact of NBTI on the Temporal Performance Degradation of Digital Circuits," IEEE Electron Device Letter, vol. 26, August 2005, pp 560562.
Conference Papers
2007
1. K. Kang, K. J Kim, Ahmad E Islam, M. Alam, and K. Roy, Characterization and Estimation of Circuit Reliability Degradation under NBTI using OnLine IDDQ Measurement,accepted in 2007 Design Automation Conference, San Diego, California, USA
2. K. Kang, M. A. Alam, and K. Roy, "Estimation of NBTI Degradation Using OnChip IDDQ Measurement," IEEE International Reliability Physics Symposium, April 2007, pp. 1016.
2006
1. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, "Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits," Design, Automation and Test in Europe, March 2006, pp. 16.
2. K. Kang, M. A. Alam, and K. Roy, "Analysis and Design of NanoScale Digital CMOS Circuits under Spatial and Temporal Reliability Degradation," SRC Student Symposium, 2006.
2005
1. M. A. Alam, H. Kufluoglu, B. C. Paul, K. Kang, and K. Roy, "On reliable circuits and systems: how reliability considerations are reshaping oxide scaling, device geometry, and VLSI algorithm," International Conference on Integrated Circuit Design and Technology, May 2005, pp. 117122.
2. A. Datta, S. Mukhopadhyay, S. Bhunia, and K. Roy, Reliability Analysis and Yield Prediction of High Performance Pipelined Circuit with respect to Delay Failures in sub100nm Technology, IEEE International Symposium on OnLine Testing, 2005.

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XII. Scaled CMOS Devices/Circuits

Journal Papers:
2008:
1. Q. Chen, N. N. Mojumder, K. Roy, "Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies," IEEE Transactions on Electron Devices, Volume 55, Issue 4, April 2008, pp. 10051012
2007:
1. A. Agarwal, K. Kang, S. Bhunia, J. D. Gallagher and K. Roy, "DeviceAware YieldCentric DualVt Design under Parametric Variations in NanoScale Technologies," accepted for publication in IEEE Transactions on VLSI.
2. A. Bansal, S. Mukhopadhyay and K. Roy, "Device Optimization Technique for Robust and Low Power FinFET SRAM Design in Nanoscale Era," To appear in IEEE Transactions on Electron Devices, June 2007.
3. A. Bansal and K. Roy, "Analytical Subthreshold Potential Distribution Model for Gate Underlap DoubleGate MOS Transistors," To appear in IEEE Transaction on Electron Devices, July 2007.
4. A. Datta, A. Goel, T. Cakici, H. MahmoodiMeimand, D. Lekshmanan and K. Roy, "Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices," to appear at IEEE Transactions of ComputerAided Design (TCAD).
2006:
1. A. Bansal, B. Paul and K. Roy, "An Analytical Capacitance Model for Interconnects using Conformal Mapping," In IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Dec. 2006, pp. 27652774.
2. B. Paul, A. Bansal and K. Roy, "Underlap DGMOS for UltraLow Power Digital Subthreshold Operation," IEEE Transactions on Electron Devices, April 2006, pp. 910913.
4. H. Ananthan and K. Roy, "Technology and Circuit Design Considerations in WidthQuantized QuasiPlanar DoubleGate SRAM," IEEE Transactions on Electron Devices, February 2006, pp 242250.
5. J. Kim and K. Roy, "A LeakageTolerant LowSwing Circuit Style in Partially Depleted SilicononInsulator CMOS Technologies," IEEE Transactions on VLSI Systems, May 2006, pp. 549552.
6. S. Mukhopadhyay, H. MahmoodiMeimand, and K. Roy, "A Novel HighPerformance and Robust Sense Amplifier Using Independent Gate Control in Sub50nm DoubleGate MOSFET," IEEE Transactions on VLSI Systems, February 2006, pp. 183192.
7. S. Mukhopadhyay, K. Kim, C.T. Chuang, and K. Roy, "Modeling and Analysis of Total Leakage Currents in Nanoscale Double Gate Devices and Circuits," IEEE Transactions on ComputerAided Design of Integrated Circuits, October 2006, pp. 20522061.
8. S. Mukhopadhyay, K. Kim, X. Wang, D. Frank, P. Oldiges, C.T. Chuang, and K. Roy, "Optimal UltraThin Body FD/SOI Device Structure Using ThinBOX for Sub50nm SRAM Design," Vol. 27, Issue 4, April 2006, pp. 284287.
9. S. Mukhopadhyay, S. Bhunia, and K. Roy, "Modeling and Analysis of Loading Effect on Leakage of NanoScale Bulk CMOS Logic Circuits," IEEE Transactions on ComputerAided Design of Integrated Circuits, August 2006, pp. 14861495.
2005:
1. A. Agarwal, S. Mukhopadhyay, C.H. Kim, A. Raychowdhury, and K. Roy, "Leakage Power Analysis and Reduction: Models, Estimation and Tools," IEEE Proceedings  Computers and Digital Techniques, May 2005, pp. 353368.
2. A. Bansal, B. Paul and K. Roy, "Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices," IEEE Transactions on Electron Devices, Feb. 2005, pp. 256262.
3. A. Bansal and K. Roy, "Asymmetric Halo CMOSFET to Reduce Static Power Dissipation with Improved Performance," IEEE Transactions on Electron Devices, March 2005, pp. 397405.
4. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A Forward BodyBiased LowLeakage SRAM Cache: Device, Circuit, and Architecture Considerations," IEEE Transactions on VLSI systems, March 2005, pp. 348357.
5. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate Estimation of Total Leakage in Nanometer Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile," IEEE Transactions on CAD of Integrated Circuits, March 2005, pp. 363381.
2004:
1. H. MahmoodiMeimand and K. Roy, "DiodeFooted Domino: A LeakageTolerant High Fanin Dynamic Circuit Design Style," IEEE Transaction on Circuits and Systems: I, pp. 495503, March 2004.
2. J. Kim and K. Roy, "DoubleGate MOSFET Subthreshold Circuit for Ultralow Power Applications," IEEE Transactions on Electron Devices, pp. 14681474 September 2004.
2003:
1. A. Agarwal, H. Li, and K. Roy, "DRG Cache: A Data Retention Gated Ground Cache for Low Power Applications," IEEE Journal of SolidState Circuits, pp. 319328, February 2003.
2. K. Roy, S. Mukhopadhyay, and H. MahmoodiMeimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in DeepSubmicron CMOS Circuits," IEEE Proceedings, pp. 305327, February 2003.
3. S. Mukhopadhyay, C. Neau, T. Cakici, A. Agarwal, C. H. Kim, and K. Roy, "Gate Leakage Reduction for Scaled Devices Using Transistor Stacking," IEEE Transactions on VLSI Systems, Aug. 2003, pp. 716730.
2002:
1. L. Wei, R. Zhang, K. Roy, Z. Chen, and D. Janes, "Vertically Integrated SOI Circuits for LowPower and HighPerformance Applications," IEEE Transactions on VLSI Systems, June 2002, pp. 351362.
2. R. Zhang and K. Roy, "LowPower HighPerformance DoubleGate Fully Depleted SOI Circuit Design," IEEE Transactions on Electron Devices, May 2002, pp. 852862.
3. R. Zhang, K. Roy, C. Koh, and D. Janes, "Exploring SOI Device Structures and Interconnect Architectures for LowPower HighPerformance Circuits," IEEE Proceedings: Computers and Digital Techniques, Vol. 149, Issue 04, July 2002, pp. 137145.
Conference Papers:
2007:
1. A. Bansal, J. Kim, K. Kim, S. Mukhopadyay, C.T. Chuang and K. Roy, "HighPerformance Device Optimization and DualVT Technology Options for DoubleGate FET," ICICDT 2007.
2. A. Bansal, J. Kim, K. Kim, S. Mukhopadyay, C.T. Chuang and K. Roy, "Optimal DualVt Design beyond 65nm Technology Node," ACEED 2007.
3. D. Lekshmanan, "Body thickness optimization and sensitivity analysis for high performance FinFETs" , DRC 2007
4. T. Cakici, K. Kim, and K. Roy, "FinFET Based SRAM Design for Low Standby Power Applications," IEEE ISQED 2007.
2006:
1. H. Ananthan, and K. Roy, "A Fully Physical Model for Leakage Distribution under Process Variations in Nanoscale DoubleGate CMOS," IEEE/ACM Design Automation Conference (DAC), July 2006.
2. Q. Chen, S. Mukhopadhyay, A. Bansal, and K. Roy, "Circuitaware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design," proceedings of IEEE Design Automation and Test in Europe (DATE), March 2006.
3. S. Gangwal, S. Mukhopadhyay and K. Roy, "Optimization of Surfaceorientation for high performance, low power and robust FinFET SRAM," CICC 2006.
4. T. Cakici, B. Jung, and K. Roy, "High Q and High Tuning Range FinFET Based Varactors for Low Cost SoC Integration," IEEE International SOI Conference, Oct. 2006, pp. 6768.
2005:
1. A. Agarwal, K. Kang, and K. Roy, "Accurate Estimation and Modeling of Total Chip Leakage Considering Inter & IntraDie Process Variations," IEEE International Conference on ComputerAided Design, November 2005, pp. 736742.
2. A. Agarwal, K. Kang, S. Bhunia, J. D. Gallagher, and K. Roy, "Effectiveness of Low Power DualVt Designs in NanoScale Technologies Under Process Parameter Variations," International Symposium on Low Power Electronics and Design, August 2005, pp. 1419.
3. A. Agarwal, K. Kang, S. Bhunia, J. Gallagher, and K. Roy, "Effectiveness of DualVt Designs in NanoScale Technologies under Process Variations," ACM/IEEE International Symposium on LowPower Electronics and Design, August 2005, pp. 1419.
4. A. Bansal, S. Mukhopadhyay and K. Roy, "Modeling and Optimization Approach to Robust and LowPower FinFET SRAM Design in Nanoscale Era," Proc. of the IEEE Custom Integrated Circuits Conference (CICC), 2005, pp. 835838.
5. A. Bansal and K. Roy, "Asymmetric Halo CMOSFET to Reduce Static Power Dissipation with Improved Performance," Proc. of the Int. Sym. Ckts And Sys., 2005, pp. 14.
6. B. Paul, A. Bansal and K. Roy, "Underlap DGMOS for Ultralow Power Digital Subthreshold Operation," Accepted for publication in the Device Research Conference, 2005, pp. 227228.
7. H. Ananthan and K. Roy, "TechnologyCircuit CoDesign in WidthQuantized QuasiPlanar DoubleGate SRAM," 2005 IEEE International Conference on Integrated Circuit and Technology, May 2005, pp. 155160.
8. H. Ananthan, A. Bansal, and K. Roy, "Analysis of DraintoBody BandToBand Tunneling in DoubleGate MOSFET," IEEE SOI Conference, October 2005.
9. K. Roy, H. MahmoodiMeimand, S. Mukhopadhyay, A. Bansal, H. Ananthan, and T. Cakici, "DoubleGate SOI Devices for LowPower and HighPerformance Applications," IEEE International Conference on ComputerAided Design (ICCAD), November 2005, Invited Paper.
10. S. Hsu, A. Agarwal, K. Roy, R. Krishnamurthy, and S. Borkar, "An 8.3 GHz Dual Supply/Threshold Optimized 32b Integer ALURegister File Loop in 90nm CMOS," ACM/IEEE International Symposium on LowPower Electronics and Design, August 2005, pp. 103106.
11. S. Mukhopadhyay, K. Kang, H. MahmoodiMeimand, and K. Roy, "Design of Reliable and SelfRepairing SRAM in Nanoscale Technologies using Leakage and Delay Monitoring," IEEE International Test Conference, November 2005, pp. 11261135.
12. S. Mukhopadhyay, H. MahmoodiMeimand, and K. Roy, "Design of High Performance Sense Amplifier Using Independent Gate Control in sub50nm DoubleGate MOSFET," IEEE International Symposium on Quality Electronic Design, pp.490495, 2005.
13. S. Mukhopadhyay, K. Kim, C.T. Chuang, and K. Roy, "Modeling and Analysis of Gate Leakage in UltraThin Oxide sub50nm Double Gate Devices and Circuits," IEEE International Symposium on Quality Electronic Design, pp. 410415, 2005.
14. S. Mukhopadhyay, K. Kim, C.T. Chuang, and K. Roy, "Modeling and Analysis of Total Leakage Currents in Nanoscale Double Gate Devices and Circuits," ACM/IEEE International Symposium on LowPower Electronics and Design, August 2005, pp. 813.
15. S. Mukhopadhyay, S. Bhunia, and K. Roy, "Modeling and Analysis of Loading Effect in Leakage of NanoScaled BulkCMOS Logic Circuits," IEEE Design and Test in Europe (DATE), pp. 224229, 2005.
16. T. Cakici, H. MahmoodiMeimand, S. Mukhopadhyay and K. Roy,"Independent Gate Skewed Logic in DoubleGate SOI Technology," IEEE International SOI Conference, Oct. 2005, pp. 8384.
2004:
1. A. Bansal, B. Paul and K. Roy, "Impact of Underlap on Gate Capacitance and Gate Tunneling Current in 16nm DGMOS Devices," Proceedings of the IEEE International SOI Conference, 2004, pp. 9495.
2. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, "Modeling and Estimation of Leakage in Sub90nm Devices," IEEE VLSI Conference, January 2004. Embedded Keynote Paper.
3. A. Agarwal, B. Paul, and K. Roy, "Process Variation in NanoScale Memories: Failure Analysis and ProcessTolerant Architecture," IEEE Custom Integrated Circuits Conference, October 2004.
4. A. Agarwal, C. H. Kim, S. Mukhopadyay, and K. Roy, "Leakage in NanoScale Technologies: Mechanisms, Impact, and Design Considerations," IEEE/ACM Design Automation Conference, pp. 611, June 2004, Invited Paper.
5. A. Agarwal, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, "90nm 6.5GHz 128X64 4Read 4Write Ported Parameter Variation Tolerant Register File," IEEE 2004 Symposium on VLSI Circuits, pp. 386387, June 2004.
6. C. H. Kim, H. Ananthan, J. Kim, and K. Roy, "Effectiveness of Using Supply Voltage as BackGate Bias in Ground Plane SOI MOSFETs," IEEE International SOI Conference, pp. 6970, Oct. 2004.
7. H. Ananthan, A. Bansal, and K. Roy, "FinFET SRAM  Device and Circuit Design Considerations," IEEE International Conference on Quality IC Design, pp. 511516, March 2004.
8. H. Ananthan, C. H. Kim, K. Roy, "LargerthanVdd forward body bias in sub0.5V nanoscale CMOS," IEEE International Symposium on LowPower Electronics and Design, pp. 813, August 2004.
9. H. MahmoodiMeimand, S. Mukhopadhyay, and K. Roy, "High Performance and Low Power Domino Logic Using Independent Gate Control in DoubleGate SOI MOSFETs," IEEE International SOI Conference, pp. 6768, Oct. 2004.
2003:
1. A. Agarwal and K. Roy, "A Noise Tolerant Cache Design to Reduce Gate and Subthreshold Leakage in the Nanometer Regime," IEEE International Symposium on LowPower Electronics and Design, pp. 1821, August 2003.
2. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A Forward BodyBiased LowLeakage SRAM Cache: Device and Architecture Considerations," IEEE International Symposium on LowPower Electronics and Design, pp. 69, August 2003.
3. C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations," IEEE International Symposium on LowPower Electronics and Design, pp. 116121, August 2003.
4. H. MahmoodiMeimand and K. Roy, "DataRetention FlipFlops for PowerDown Applications," IEEE International Symposium on Circuits and Systems, May 2003.
5. H. MahmoodiMeimand and K. Roy, "DualEdge Triggered Level Converting FlipFlops," IEEE International Symposium on Circuits and Systems, May 2003.
6. J. Kim and K. Roy, "Double Gate MOSFET Subthreshold Logic for UltraLow Power Applications," IEEE International SOI Conference, pp. 9798, October 2003.
7. S. Mukhopadhyay and K. Roy, "Modeling and Estimation of Total Leakage Current in NanoScaled CMOS Devices Considering the Effect of Process Variation," IEEE International Symposium on LowPower Electronics and Design, pp. 172175, August 2003.
8. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling,'' IEEE/ACM Design Automation Conference, pp. 169174, June 2003.
9. T. Cakici, A. Bansal and K. Roy, "A Low Power Four Transistor Schmitt Trigger for Asymmetric Double Gate FullyDepleted SOI Devices," IEEE International SOI Conference, Oct. 2003, pp. 2122.
2002:
1. A. Agarwal, H. Hai, and K. Roy, "DRGCache: A Data Retention GatedGround Cache for Low Power," ACM/IEEE Design Automation Conference, June 2002, pp. 473478.
2. H. MahmoodiMeimand and K. Roy, "SelfPrecharging FlipFlop (SPFF): A New Level Converting FlipFlop," European SolidState Circuits Conference (ESSCIRC), September 2002, pp. 407410.
3. J. Kim and K. Roy, "SenseAmplifierless DCSL:A Circuit Style Tolerant to Folating Body Effects in PD/SOI," European SolidState Circuits Conference (ESSCIRC), September 2002, pp. 271274.
4. J. Kim and K. Roy, "SOISpecific TriState Inverter and Its Application," IEEE International SOI Conference, pp. 145146, 2002.
5. J. Kim, R. Joshi, C. Chuang, and K. Roy, "SOIOptimized 64bit HighSpeed CMOS Adder Design," IEEE VLSI Circuits Symposium, June 2002.
6. T. Cakici and K. Roy, "Current Mirror Evaluation Logic: A New Circuit Style for High
Fanin Dynamic Gates," ESSCIRC 2002, pp. 395398.
2001:
1. J. Kim and K. Roy, "A Leakage Tolerant High Fanin Dynamic Circuit Design Technique," European Solid State Circuits Conference, September 2001.
2. R. Zhang, K. Roy, D. Janes, and C. Koh, "Exploring SOI Device Structures and Interconnect Architectures for 3Dimensional Integration," ACM/IEEE Design Automation Conference, 2001, pp. 846851.
3. R. Zhang, K. Roy, and D. Janes, "DoubleGate FullyDepleted SOI Transistors for NanoTechnology Regime," ACM/IEEE International Symposium on Low Power Electronics and Design, Aug. 2001, pp. 213218.

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XIII. VLSI Test and Fault Tolerance

Journal Publications:
2006
1. S. Ghosh, S. Bhunia, A. Raychowdhury and K. Roy, A novel delay fault testing methodology using lowoverhead builtin delay sensor, IEEE Trans. Computer Aided Design, Dec 2006.
2005
1. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Efficient Testing of SRAM with Optimized March Sequences and a Novel DFT Technique for Emerging Failures due to Process Variations, IEEE Trans. on VLSI, Dec. 2005.
2. S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh and K. Roy, LowPower Scan Design Using First Level Supply Gating, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 384395, March, 2005.
3. S. Bhunia and K. Roy, Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current, Journal of Electronic Testing: Theory and Applications, pp. 147159, 2005.
4. S. Mukhopadhyay, H. Mahmoodi and K. Roy, Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in NanoScaled Technologies, IEEE Transactions on ComputerAided Design of Integrated Circuits, pp. 18591880, Dec. 2005.
2004
1. N. Sirisantana, B. Paul, and K. Roy, Enhancing yield at the end of the technology roadmap, IEEE Design and Test, pp. 563571, Nov. Dec. 2004.
2003
1. A. Keshavarzi, K. Roy, C. Hawkins, and V. De, MultipleParameter CMOS IC Testing with Increased Sensitivity for IDDQ, IEEE Transactions on VLSI Systems, pp. 863870, Oct. 2003.
2002
1. Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, IDDQ Testing for Deep SubMicron IC's: Challenges and Solutions, IEEE Design and Test, pp. 2433, MarchApril, 2002.
2. A. Keshavarzi, K. Roy, J. Tschantz, S. Narendra, A. Daasch, C. Hawkins, and V. De, Impact of Leakage and Process Variation on CurrentBased Testing for Future
Scaled CMOS Circuits, IEEE Design and Test, pp. 3643, Sep.Oct., 2002.
2001
1. A. Keshavarzi, K. Roy, and C. Hawkins, Intrinsic Leakage in Deep Submicron IC's  Measurement Based Test and Power Solutions, IEEE Design and Test, pp. 4249, Jan.Feb., 2001.
2. Z. Chen, L. Wei, and K. Roy, On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques, IEEE Transactions on VLSI Systems, pp. 718725, Oct. 2001.
2000
1. X. Zhang, K. Roy, and S. Bhawmik, Low Power Weighted Random Pattern Testing, IEEE Transactions on ComputerAidedDesign, pp. 13631369, Nov. 2000.
2. K. Muhammad and K. Roy, Fault Detection and Location Using IDD Waveform Analysis, IEEE Transactions on ComputerAidedDesign, pp. 13891398, Nov. 2000.
Conference Publications:
2007
1. S. Ghosh, S. Bhunia, and K. Roy, A Fault Tolerant Technique for Improved Yield in Nanometer Technologies by Adaptive Clock Stretching, International OnLine Test Symposium, 2007.
2006
1. S. Ghosh, S. Mukhopadhyay, K. Kim and K. Roy, Selfcalibration technique for reduction of hold failures in lowpower nanoscaled SRAM, Design Automation Conference, 2006.
2. S. Ghosh, S. Bhunia, A. Raychowdhury and K. Roy, Delay fault localization in testperscan BIST using Builtin Delay Sensor, International OnLine Testing Symposium, 2006.
3. A. Goel, S. Bhunia, H. Mahmoodi and K. Roy, A LowOverhead Design of SoftErrorTolerant Scan FlipFlop with EnhancedScan Capability, ASPDAC, 2006.
4. S. Mukhopadhyay, A. Agarwal, Q. Chen and K. Roy, SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design, IEEE Custom Integrated Circuits Conference, Sep. 2006. [Invited Paper]
2005
1. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Modelling and Testing of SRAM for New Failure Mechanisms due to Process Variations in Nanoscale CMOS, proceedings of IEEE VLSI Test Symposium (VTS), May 2005.
2. S. Ghosh, S. Bhunia and K. Roy, Shannon expansion based supplygated logic for improved power and testability, Asian Test Symposium, 2005.
3. M. Meterelliyoz, H. Mahmoodi and K. Roy, A Leakage Control System for Thermal Stability During BurnIn Test, International Test Conference (ITC), 2005.
4. S. Mukhopadhyay, K. Kang, H. Mahmoodi and K. Roy, Design of Reliable and SelfRepairing SRAM in Nanoscale Technologies using Leakage and Delay Monitoring, International Test Conference (ITC), 2005.
5. P. Ndai, A. Agarwal, Q. Chen and K. Roy, A Soft Error Monitor Using Current Switching Detection (in SRAM) , ICCD 2005.
6. A. Raychowdhury, S. Ghosh and K. Roy, A Novel Onchip Delay Measurement Hardware for Efficient SpeedBinning, International OnLine Testing Symposium, 2005.
7. A. Raychowdhury, S. Ghosh, S. Bhunia, D. Ghosh and K. Roy, "A Novel Delay Fault Testing Methodology using Lowoverhead Builtin Delay Sensor, European Test Symposium, 2005.
8. S. Bhunia, H. Mahmoodi, and K. Roy, Power Reduction in TestPerScan BIST with Supply Gating and Efficient Scan Patitioning, IEEE International Symposium on Quality Electronic Design, pp.453458, 2005.
9. S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, A Novel LowOverhead Delay Testing Technique for Arbitrary TwoPattern Test Application, IEEE Design and Test in Europe (DATE), pp.11361141, 2005.
2004
1. S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh and K. Roy, A Novel Low Power Scan Design Technique Using Supply Gating, ICCD, 2004, [Best Paper Award].
2. S. Bhunia, A. Raychowdhury, and K. Roy, Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current, IEEE International Conference on Quality IC Design, pp. 389394, March 2004.
3. S. Mukhopadhyay, H. MahmoodiMeimand, and K. Roy, Modeling and Estimation of Failure Probability due to Parameter Variations in NanoScaled SRAMs for Yield Enhancement, IEEE 2004 Symposium on VLSI Circuits, pp. 6467, June 2004.
2003
1. S. Bhunia and K. Roy, Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Current, 4th IEEE Latin American Test Workshop, pp. 183187, February 2003. [Best Paper Award]
2. K. Roy, T.M. Mak, and K.T. Cheng, Test Considerations for Nanometer Scale CMOS Circuits, IEEE VLSI Test Symposium, May, 2003. [Invited Paper]
3. D. Ghosh, S. Bhunia, and K. Roy, Multiple Scan Chain Design Technique for Power Reduction During Test Application in BIST, 18th International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 191198, 2003.
2002
1. Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, IDDQ Testing for Deep Submicron CMOS ICs: Challenges and Solutions, IEEE Latin America Test Workshop, Feb. 2002.
2. S. Bhunia and K. Roy, Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis, Design Automation and Test in Europe (DATE), pp. 1118, March, 2002.
3. S. Bhunia and K. Roy, Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform, IEEE VSLI Test Symposium, pp. 302 307, April, 2002.
4. S. Bhunia, K. Roy, and J. Segura, A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Localization, ACM/IEEE Design Automation Conference, pp. 361366, June, 2002.
5. S. Bhunia, H. Li, and K. Roy, A High Performance IDDQ Testable Cache for Scaled CMOS Technologies, IEEE Asian Test Symposium, pp. 157162, November, 2002.
2001
1. B. Paul, S.H. Choi, Y. Im, and K. Roy, Design Verification and Robust Design Technique for CrossTalk Faults, Asian Test Symposium, pp. 449454, November, 2001.
2000
1. Z. Chen, L. Wei, and K. Roy, On Effective IDDQ Testing of LowVoltage CMOS Circuits Using Leakage Control Techniques, IEEE International Symposium on Quality of IC Design, pp. 181188, 2000. [Best Paper Award]
2. X. Zhang and K. Roy, LowPower BIST with Peak Power Vector Elimination, International Symposium on Quality of IC Design, pp. 425432, 2000.
3. K.T. Cheng, S. Dey, M. Rodgers, and K. Roy, Test Challenges for Deep Submicron Technologies, ACM/IEEE Design Automation Conference, pp. 142149, 2000. [Invited Embedded Tutorial]
4. X. Zhang and K. Roy, Power Reduction in TestPerScan BIST, IEEE International OnLine Test Workshop, pp. 133138, 2000.
5. A. Keshavarzi, K. Roy, M. Sachdev, C. Hawkins, K. Soumyanath, and V. De, MultipleParameter CMOS IC Testing with Increased Sensitivity for IDDQ, IEEE International Test Conference, pp. 10511059, 2000.

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XIV. Ultralow Voltage Subthreshold Circuits and systems

Journal Publications:
2005
1. A.Raychowdhury, B. Paul, S. Bhunia, and K. Roy, Computing with Subthreshold Leakage: Device/Circuit/Architecture CoDesign for UltralowPower Subthreshold Operation, IEEE Transactions on VLSI Systems, November 2005, pp. 12131224 (no. 105)
1. B. Paul, A. Raychowdhury, and K. Roy, Device Optimization for Digital Subthreshold Logic Operation, IEEE Transactions on Electron Devices, February 2005, pp. 237247. (no. 87)
2004
1. J. Kim and K. Roy, DoubleGateMOSFET Subthreshold Circuit for Ultralow Power Applications,IEEE Transactions on Electron Devices, pp. 14681474 September 2004. (no. 82)
2003
1. C. H. Kim, H. Soeleman, and K. Roy, "UltraLow Power DLMS Adaptive Filter for Hearing Aid Applications", IEEE Transactions on VLSI Systems, pp. 10581067, December 2003 (no. 76)
O 2005 IEEE Circuits and Systems Society Outstanding Young Author Award
2001
1. H. Soeleman, K. Roy, and B. Paul, "Robust SubThreshold Logic for UltraLow Power Operation", IEEE Transactions on VLSI Systems, Special issue on lowpower design, pp.9099, February 2001.(no. 52)
Conference Publications:
2006
1. B. Paul, and K. Roy, Optimizing Oxide Thickness for Digital Subthreshold Operation, IEEE Device Research Conference, 2006, pp. 6364. (no 423)
2. A. Raychowdhury, B. Paul, S. Bhunia, and K. Roy, Computing With Subthreshold Leakage: A Comparative Study of Bulk and SOI Technologies, IEEE Design and Test in Europe (DATE), March 2006(no. 412)
2005
1. A.Raychowdhury, S. Mukhopadhyay, and K. Roy, "A Feasibility Study of Subthreshold SRAM Across Technology Generations", IEEE International Conference on Computer Design (ICCD), October 2005.(no. 395)
2004
1. B.C. Paul, A. Raychowdhury, K. Roy, Device Optimization for UltraLow Power Digital SubThreshold Operation, IEEE International Symposium on LowPower Electronics and Design, pp.96101, August 2004. (no. 359)
2. B. Paul and K. Roy, "Device Optimization for Digital Subthreshold Operation", IEEE Device Research Conference, pp. 113114, June 2004. (no. 345)
2003
1. J. Kim and K. Roy, "DoubleGate MOSFET Subthreshold Circuit for Ultralow Power Applications", IEEE Transactions on Electron Devices, pp. 14681474, September 2004.(no. 323)
2001
1. B. Paul, H. Soeleman, and K. Roy, "An 8X8 SubThreshold Digital CMOS Carry Save Array Multiplier", European Solid State Circuits Conference, September 2001.
2. H. Soeleman and K. Roy, "SubDomino Logic: UltraLow Power Dynamic SubThreshold Logic", IEEE International Conference on VLSI Design, pp. 211214, 2001.
2000
1. H. Soeleman, K. Roy, and B. Paul, "Robust UltraLow Power Subthreshold DTMOS Logic", IEEE International Symposium on LowPower Electronics and Design, pp. 2530, 2000
2. H. Soeleman and K. Roy, "Digital CMOS Logic Operation in the SubThreshold Region", IEEE Great Lakes Symposium on VLSI, pp. 107112, March 2000.
Patents:
1. J. Kim and K. Roy, "Double Gate MOSFET Subthreshold Circuit for Ultralow Power Applications", US Patent Pending
2. J. P. Kulkarni and K. Roy SRAM cell with builtin process tolerance patent filed with Purdue Research Foundation, March 2007

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