Tiwei Wei

Tiwei Wei

Assistant Professor of Mechanical Engineering

School of Mechanical Engineering
Purdue University
585 Purdue Mall
West Lafayette, IN 47907-2088

Office: Birck 2044

Phone: 650-505-6084
Other: 6505056084


  • Postdoc. Stanford University, '22
  • Ph.D. IMEC & KU Leuven, '20
  • Researcher: Tsinghua University, '14; HKUST, '15
  • M.S. Joint CQUPT and Tsinghua University, '12

Research Interests

  • Addressing the process integration and reliability challenges for fine-pitch, high-density advanced semiconductor packaging techniques: Monolithic 3D Integration, Heterogeneous 2.5D interposer and 3D Integration, Microsystem integration, Fan-out packaging and Embedded packaging
  • Thermomechanical modeling and characterization of advanced devices and packages: chip package interactions, FEM modeling, and thermal stress metrology
  • "Smart-controlled cooling” with advanced manufacturing technologies using MEMS and 3D packaging: Active flow control for dynamic power profiles
  • Advanced heat sink design optimization and fabrication: Topology optimization and Additive manufacturing of the package level cooling system
  • Efficient thermal packaging materials: high thermal conductivity TIM (thermal interface materials), and underfill, efficient 3D bonding interface thermal materials

Awards and Recognitions

  • Vice chair and Executive committee, IEEE-EPS Silicon Valley Area Chapter (2022 - Present)
  • Session chair, Technical program committee, IEEE 3DIC 2021 Conference (2021 - Present)
  • Session chair, Organization committee, IEEE REPP (Reliability for Electronics and Photonics Packaging) (2021 - Present)
  • Technical program committee, Advanced Packaging Subcommittee in Electronics System-Integration Technology Conferences (ESTC) 2022 (2022 - Present)
  • Technical committee, IEEE EPS-Reliability (2021 - Present)

Selected Publications

Wei, T. W.*, Oprins, H., et al., Heat Transfer and Friction Factor Correlations for Direct on-Chip Microscale jet impingement Cooling with Alternating Feeding and Draining Jets, Int. J. Heat Mass Transf, 2021, Volume 182, 121865.

Wei, T. W.*, All-in-one design integrates microfluidic cooling into electronic chips, Nature, News and Views, 585, 188-189 (2020) doi: 10.1038/d41586-020-02503-1. (Invited)

Wei, T. W.*, Oprins, H., Cherman, V., Qian, J., De Wolf, I., Beyne, E., & Baelmans, M. (2018). High-Efficiency Polymer-Based Direct Multi-Jet Impingement Cooling Solution for High-Power Devices. IEEE Transactions on Power Electronics, 34(7), 6601-6612.

Wei, T. W.*, Oprins, H., Cherman, V., Van der Plas, G., De Wolf, I., Beyne, E., & Baelmans, M. (2017, December). High efficiency direct liquid jet impingement cooling of high-power devices using a 3D-shaped polymer cooler. In 2017 IEEE International Electron Devices Meeting (IEDM) (pp. 32-5). IEEE.

Wei, T. W.*, Oprins, H., Beyne, E., & Baelmans, M. (2019, May). First Demonstration of a Low Cost/Customizable Chip Level 3D Printed Microjet Hotspot-Targeted Cooler for High Power Applications. In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) (pp. 126-134). IEEE.

Wei, T. W., Lin, Z., Asheghi, M., & Goodson, K. E*., “Micro-channel Cooling Technique to Minimize Thermal Deformation of the X-ray and High-power Laser Optics”, International Conference on Synchrotron Radiation Instrumentation (SRI) 2022.

Wei, T. W., Qiu X., Lo J C C, Ricky L.*. Wafer level bumping technology for high voltage LED packaging[C]//2015 10th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT). IEEE, 2015: 54-57.

Wei, T. W., Cai J.*, et al. Performance and reliability study of TGV interposer in 3D integration[C]//2014 IEEE 16th Electronics Packaging Technology Conference (EPTC). IEEE, 2014: pp. 601-605.

Wei, T. W., Wang, Q., Liu, Z., Li, Y., Wang, D., Wang, T., & Cai, J*. (2012, December). A 3D integration testing vehicle with TSV interconnects. In 2012 14th International Conference on Electronic Materials and Packaging (EMAP) (pp. 1-5). IEEE.

Wei, T. W., Cai J.*, Wang Q., et al. Copper filling process for small diameter, high aspect ratio through silicon via (TSV)[C]//2012 13th International Conference on Electronic Packaging Technology & High Density Packaging. IEEE, 2012: 483-487. (Outstanding Paper Award)