Ravi Mahajan — Lecture
|Event Date:||November 4, 2021|
|Speaker:||Ravi Mahajan, Intel Fellow, High Density Interconnect Pathfinding, ASME Fellow, IEEE Fellow, VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT,
Assembly Technology, Intel Corporation
|Location:||FRNY Atrium and Zoom|
|School or Program:||Mechanical Engineering
Advanced Packaging Architectures and Technologies for Heterogeneous Integration
Advanced packaging technologies are critical enablers of Heterogeneous Integration (HI) because of their importance as compact, power efficient platforms. This talk will first review the evolution of packaging to set context and describe the increasing value of packaging as an HI platform. Different packaging architectures will be compared on the basis of their physical interconnect capabilities, power delivery, power removal, and high bandwidth signaling capabilities. Key features in leading edge 2D and 3D technologies, will be described and a roadmap for their evolution will be presented. Specific examples, showing how product implementations take advantage of these technologies, to provide an unprecedented level of performance, will be used to describe the challenges and opportunities in developing robust advanced package architectures. In addition to performance characteristics, this talk will also illustrate key opportunities and challenges in materials development, manufacturability and reliability, and describe how well defined industry-academia partnerships can continue to ensure successful evolution of the HI roadmap.
Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes including 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi joined Intel in 1992 after earning Ph.D. in Mechanical Engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award For Excellence and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE. Link to bio.
Hosted by College of Engineering, Mechanical Engineering, and Electrical and Computer Engineering