[BNC-grads-list] Prelim exam tomorrow

[MD Abdul Wahab]

Hello All,

I would like to invite you for my prelim talk tomorrow.
Here are the details.

Thesis title: Computational modeling and design of aligned-array nanotube/nanowire transistors for high speed nanoelectronic applications

Examination Date: Friday, January 31, 2014
Examination Time: 9:30 AM
Examination Location: Birck Nanotechnology Center (BNC) Room 1001

Abstract:
As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is moving toward the 3D device architectures, such as FinFETs, starting at the 22 nm technology node. The FinFET will likely scale down to 10 nm, but since physical limits such as the short channel effect (SCE) and/or surface roughness scattering may dominate; it may be difficult to scale Si FinFET below 10 nm. Other 3D FET structures, based on an array of single-wall carbon nanotube (SWNT) or gate-all-around (GAA) InGaAs nanowire (NW), have higher drive current and could be a viable technology option below 10 nm. The goal of this thesis is two-fold: first, to help design SWNT devices by considering theoretical merits of new strategies of removing metallic (m-) SWNTs, while retaining semiconducting (s-) SWNTs in chemically pristine form, and then achieving  high density (>150 /µm)  by  multiple transfer printing. The second goal is to analyze the reliability of these array transistors (for SWNT: random and correlated breakdown (CBD) due to the electrostatic cross-talk; for InGaAs: degradation due to the negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI)).

We have developed a phenomenological 3D self-consistent computation model which deals with electrostatics (drift-diffusion with Poisson) and heat transport to analyze process-performance-reliability of nanotube and nanowire transistors. Through this model, we have made the following contributions. (i) Characterization of the s-SWNTs diameter distribution through electroluminescence. (ii) Modeling strategies of soft-burning toward filtering m-SWNTs using thermocapillary flow mechanism with two independent heat sources: DC and microwave. (iii) Modeling electrostatic control of gate over SWNT density. (iv) Modeling electrostatic cross-talk in high-density carbon nanotubes to explore the density limit to avoid correlated breakdown in channel and false programming in phase-change-memory. I work closely with my colleagues from UIUC to systematically validate the results with experiments. In future work, I will have two major themes:  First, I will generalize 3D partial-gate-FET with aligned-array carbon nanotube as channel for bio-sensing application. Second, I will analyze variability and reliability of multiple nanowires GAA-InGaAs 3D and 4D transistors. For multiple nanowires, nanowire to nanowire variability may change the performance of the device. This variability may enhance because of the self-heating. Important reliability concerns (e.g., PBTI, HCI, and NBTI) will be analyzed.

Our studies establish a method by which high density aligned-array of s-SWNTs (in chemically pristine form) are available as channel materials for logic applications at sub 10 nm technology node. The analysis of variability and reliability of the multiple nanowires GAA-InGaAs transistors will help to improve the performance and lifetime of the integrated circuits based on the technology.


Regards,
Abdul Wahab

-- 
Muhammad A. Wahab
Graduate Research Assistant
Prof. Muhammad Ashraful Alam's CEED Group
School of Electrical and Computer Engineering
Purdue University, West Lafayette, IN
Website: http://web.ics.purdue.edu/~mwahab/