[BNC-all] National Nano Device Laboratories, Taiwan (NDL) Seminar, Dec. 1st @ 11am in MRGN 129

[Turner, Jaime J]

National Nano Device Laboratories, Taiwan (NDL) Seminar
DECEMBER 1, 2017
11:00 AM - 12:00 PM
MRGN 129
NDL Introduction: beyond more than Moore CMOS (11:00am-11:20am)
Prof. Wen-Kuan Yeh, Director of National Nano Device laboratories (NDL), Taiwan
NDL (National Nano Device Laboratories) is an important place to cultivate high-level technology talents for semiconductor and nano techniques in Taiwan.  It has become a national open nano device process test environment, and provided a unique open experiment research environment for comprehensive turnkey consignment services. As MOSFETs are scaled down to sub-10nm and below, power consumption is the major limitation to maintain device performance well.
Development of Ge NW FETs (11:20am-11:35am)
Dr. Yao-Jen Lee, National Nano Device laboratories (NDL), Taiwan
Germanium is attractive for the future technology node application because of its two times higher electron mobility and 4 times higher hole mobility than that of Si counterpart. . The lower band gap of Ge also allows the supply voltage scalability to satisfy the post-Si CMOS era. How-ever, the Ge MOSFET tech-nology is facing several serious challenges, including fast n-type dopant diffusion, high junction leakage, EOT scaling, Dit reduction and enormous dislocation defects in the Ge epi-layer on Si substrates because of the large lattice mismatch to Si. Herein, we propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge gate-all-around (GAA) nanowire (NW) FETs.
Ge Devices with Ferroelectric Hf1-xZrxO Gate Stack (11:35am-11:50am)
Dr. Chun-Jung Su, National Nano Device laboratories (NDL), Taiwan
Germanium (Ge) has been widely studied as a potential alternative channel material for sub-3nm technology node because of its high carrier mobility and process compatibility. In order to meet the requirements of steep subthreshold slope (SS) and low VDD operation for device scaling, the ferroelectric (FE) gate stack with negative capacitance (NC) effects has been proposed to tackle the fundamental thermionic limit of 60 mV/decade SS without causing loss to the drive current.

Jaime Turner
Administrative Assistant to the Director
Birck Nanotechnology Center | Room 1027 | W. Lafayette, IN
Office:  765.494.3509 | Fax: 765.496.8383 | Email: jjturner at purdue.edu<mailto:jjturner at purdue.edu>
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