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Why Opens Should Be Explicitly Targeted in "Zero Defect" Testing

Event Date: September 11, 2017
Speaker: Dr. Adit D. Singh
Speaker Affiliation: Auburn University
Type: VLSI Research Area Seminar
Time: 11:00am
Location: MSEE 239
Contact Name: Professor Anand Raghunathan
Contact Phone: 765-49-43470
Contact Email: raghunathan@purdue.edu
Priority: No
School or Program: Electrical and Computer Engineering
College Calendar: Show

Abstract

The reliability requirements for electronics deployed in cars, and other autonomous control applications, increasingly demand integrated circuits tested to a stringent “zero defect” test standard. This is very challenging in view of the inherent exponential complexity of test. More extensive testing of ICs often reveal test escape rates much higher than those initially estimated. For example, newly developed cell-aware test methods have received much publicity because they have been shown to detect significant defectivity missed by traditional stuck-at and transition delay fault (TDF) testing. At ITC 2012, Hapke et al. reported test escape levels of 885 defective parts per million (DPM) in a 32 nm high volume notebook processor part tested using industry best practice 5-detect stuck-at and 5-detect TDF tests. Importantly, most of these test escapes were observed to cause failure in actual system application, indicating a potentially serious field reliability issue. Careful analysis indicates that the large majority of the additional fallout from cell aware tests applied to a range of circuits are open defects. In this presentation we make the case that open defects should be directly targeted by ATPG aimed at generating the most cost effective test sets. Since two-pattern tests for open defects also cover corresponding TDFs, the increase in test set size over current stuck-at and TDF is modest, while such tests can significantly improve actual defect coverage in production. Additionally, if very low defect levels are required, a new class of hazard activated open defects must also be targeted. These appear redundant in steady state signal analysis, but can, in fact, cause circuit failures. Today, even the most advanced fault models miss hazard activated opens because they are very difficult to defect. Reliable testing of these defects remains an open research problem.

Biography

Adit D. Singh received the B.Tech from the Indian Institute of Technology Kanpur, and the M.S. and Ph.D. from Virginia Tech, all in Electrical Engineering. He is currently James B. Davis Professor of Electrical and Computer Engineering at Auburn University, USA. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing.  He has published over two hundred and fifty research papers, served as a consultant to several semiconductor companies, and holds international patents that have been licensed to industry.  He has had leadership roles as General Chair/Co-Chair/Program Chair in dozens of international VLSI design and test conferences, and on the editorial boards of several journals. He served two elected terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and on the Board of Governors (2011-15) of the IEEE Council on Design Automation (CEDA). Singh is a Fellow of IEEE and a Golden Core member of the IEEE Computer Society.