Testing Low-Power Integrated Circuits: Challenges and Solutions

Event Date: September 16, 2013
Speaker: Dr. Srivaths Ravi
Speaker Affiliation: Texas Instruments
Sponsor: VLSI Area Seminar
Time: 2:00 PM
Location: EE 317
Contact Name: Professor Anand Raghunathan
Contact Phone: (765) 494-3470
Contact Email: raghunathan@purdue.edu
Open To: ACCEPTABLE FOR ECE 694A

The push for portable, battery-operated, and "cool-and-green" electronics has elevated power consumption as the defining metric of integrated circuit (IC) design.  Testing ICs built for such applications requires judicious consideration of test power implications on various aspects of the design cycle (e.g., packaging and power grid design), test engineering (multi-site ATE power supply limitations and board design), power-aware test planning (DFT and ATPG), and developing the enabling EDA tool infrastructure (SW for estimation, reduction and low-power test generation). Furthermore, with power optimization and power management techniques becoming "de-facto" in almost all 45nm and lower chips, systematic testing of these structures and the device in the presence of these structures becomes mandatory.  This talk is intended to provide a bird's eye view of low-power IC testing covering key challenges, commonly deployed solutions and emerging topics of interest in chips developed today.

 

Biography

Dr. Srivaths Ravi is a Design Manager, and Member of Group Technical Staff with the Processor Group at Texas Instruments, India. He most recently led the implementation and tape out of a secure, low-power chip developed by TI's Sitara business unit. Prior to his current role, he has led the DFT implementation in TI's Sitara products and has also been responsible for furthering test methodology initiatives in power-aware test, scan compression, and ATPG, and test tool deployment across different business units.

Prior to joining TI, Dr. Ravi was a research staff member with NEC Laboratories America, Princeton, where he worked in the areas of test, low power EDA, and embedded security. He has multiple publications in leading conferences and journals, and has received seven best paper awards and seven granted patents. Dr. Ravi received the B.Tech. degree in Electrical and Electronics Engineering and the Siemens Medal from the Indian Institute of Technology, Madras, India in 1996 and the M.A. and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, NJ. He is a Senior Member of IEEE.