Processor Design for Exascale Computing
|Event Date:||July 10, 2017|
|Speaker Affiliation:||AMD Research|
|School or Program:||Electrical and Computer Engineering
The US Department of Energy’s exascale computing initiative aims to build supercomputers to solve a wide range of HPC problems, including emerging data science and machine learning problems. The talk will first cover the requirements for exascale computing and highlight various challenges that need to be addressed. The talk will then give an overview of research on various techniques and technologies that AMD is pursuing to design an Exascale Heterogeneous Processor (EHP) to address these challenges and serve as the basic building block of an exascale supercomputer.
Brad Beckmann has been a member of AMD Research since 2007 and works in Bellevue, WA. Brad completed his PhD degree in the Department of Computer Science at the University of Wisconsin-Madison in 2006 where his doctoral research focused on physical and logical solutions to wire delay in CMP caches. While at AMD Research, he has worked on numerous projects related to memory consistency models, cache coherence, graphics, and on-chip networks. Currently, his primary research focuses on GPU compute solutions and broadening the impact of future AMD Accelerated Processing Unit (APU) servers.