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Data Modulation and Retrieval in NAND Flash Memories

Event Date: March 10, 2016
Speaker: Borja Peleato-Inarrea
Speaker Affiliation: ECE, Purdue University
Time: 3:00pm
Location: MSEE 239
Contact Name: Professor James Krogmeier
Contact Phone: 765-49-43530
Contact Email:
Priority: No


For several decades, CPUs have doubled their speed every two years following Moore’s law, but traditional spinning disk storage has not been able to keep up with this trend: hard drives have steadily increased their capacity, but not their speed. Recently, flash-based Solid State Drives (SSD’s) have emerged as a faster and more efficient alternative to hard drives but their higher cost is still an obstacle for their widespread use. Manufacturers have significantly reduced the cost by aggressively scaling the technology but this reduction has lead to noisier writing and unreliable reading. It is thus a signal processing challenge to write and read back reliably. This talk proposes methods to overcome this challenge.  The talk will start with an overview of the NAND flash read and write channels, focusing on the data integrity issues that they present and the tools that flash controllers have at their disposal to address those issues, such as adjusting the read thresholds and voltage levels. Next, I will show that the problem of selecting the read thresholds is equivalent to the quantization of the inputs to a mismatched decoder. This formulation will be used to derive a lower bound on the read channel capacity and to construct a dynamic programming algorithm for solving the problem. Then, I will propose a new data representation scheme that uses orthogonal codes to spread each information symbol over multiple flash cells. This scheme can be used to increase the memory’s robustness against impulsive noise and inter-cell interference, to increase the memories’ lifetime, and to hide information in an already written flash memory. Finally, I will present a technique for combining multiple pages into a single read and show the advantages that it offers in a few different scenarios.



Borja  Peleato  is  a  Visiting  Assistant  Professor  in  the  school  of  Electrical  and  Computer Engineering at  Purdue  University.  His  current  research  interests  include  signal  processing and channel coding for non-volatile storage, distributed optimization, wireless communications, and financial  networks.  He  received  his  B.S.  from  the  Universitat  Politecnica  de  Catalunya  in Barcelona, Spain, writing the final thesis as a visiting student at the Massachusetts Institute of Technology in 2006, and received his Ph.D. in Electrical Engineering from Stanford University in 2013. After his Ph.D. work, he spent one year in Proton Digital Systems as a Senior Flash Channel Architect, where he was in charge of flash memory characterization, LDPC code construction, and signal processing routines. Borja is the recipient of a "La Caixa" graduate fellowship award.