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Circuit and Microarchitecture Co-Design for Power-Efficient Multi-core Processors

Event Date: March 8, 2012
Speaker: Professor Nam Sung Kim
Speaker Affiliation: University of Wisconsin-Madison
Time: 3:00 PM
Location: EE 317
Contact Name: Professor Kaushik Roy
Contact Phone: (765) 494-2361
Contact Email:

In this talk, I present three circuit and microarchitecture co-design techniques for power-efficient multi-core processors. First, I present  a technique for last-level-caches (LLCs) supporting low minimum operating voltage (VDDMIN) cost-effectively. In this technique, I exploit (i) the DVFS characteristics of workloads running on high-performance processors, (ii) the trade-off between SRAM cell size and VDDMIN, and 3) the fact that at lower voltage/frequency operating states the negative performance impact of having a smaller LLC capacity is reduced. My proposed LLC architectures provide the same maximum performance and VDDMIN as the conventional architecture, while reducing the total LLC cell area by 15%-19% with negligible average runtime increase. Second, I present a technique supporting multiple voltage domains cost-effectively. This technique is based on the observations that (i) core-to-core voltages variations are relatively small when the voltages are optimized to maximize performance under a power constraint; (ii) per-core power-gating devices can be modified to serve as low-cost voltage regulators that can provide high efficiency in situations like (i) by augmenting them with small circuits; and (iii) core-to-core frequency/power variations are large due to within-die process variations. Our experimental results show that processors adopting our technique can achieve power efficiencies as high as ones using per-core on-chip switching voltage regulators with much less cost.


Biography:  Nam Sung Kim is an assistant professor at the University of Wisconsin-Madison. He was with Intel's Microprocessor Technology Lab (MTL) as a senior research scientist from 2004 to 2008 after he received his Ph.D. degree in Computer Science and Engineering from the University of Michigan-Ann Arbor in 2004. He has published more than 70 technical papers in the field of digital circuit, processor architecture, and CAD. He also has served several prominent international conferences as a technical program committee member. He was a recipient of IEEE Design Automation Conference (DAC) Student Design Contest Award in 2001, Intel Fellowship in 2002, and IEEE International Conference on Microarchitecture (MICRO) Best Paper Award in 2003, NSF CAREER Award in 2010, and IBM Faculty Award in 2011. His current research interest is designing robust, low-power computing systems in nanoscale technology