Nonvolatile Flash Memory: An Overview

Event Date: April 23, 2008
Speaker: Souvik Mahapatra
Speaker Affiliation: ITT Bombay, India
Sponsor: Network for Computational Nanotechnology
Time: 2:30 PM
Location: EE 317
Open To: Acceptable for ECE694A

In this talk, we will review the memory program and erase operation of floating gate flash cells under both NAND and NOR architecture. The reliability issues, such as cycling endurance, retention and array disturbs will be reviewed next. Finally, the floating gate cell scaling challenges will be discussed, and flash memories having newer charge storage node (nitride, metal nanocrystals) will be reviewed.



Souvik Mahapatra received his PhD in Electrical Engineering from IIT Bombay, India in 1999. He was with Bell Laboratories, Lucent technologies, Murray Hill, NJ, USA during 2000-01. Since 2002 he is with the Department of Electrical Engineering, IIT Bombay, India, and presently holds the post of Associate Professor. His research interests are CMOS device and Flash memory scaling and reliability. He has published more than 75 papers in international journals and conferences, delivered invited talks in major international conferences including the IEDM, and was a tutorial speaker at IRPS. He is a senior member of IEEE