Milliwatt Chips: The Viable Scalability Path for Data Centers

Event Date: February 18, 2010
Speaker: Professor Babak Falsafi
Speaker Affiliation: Computer Science, Epfl, Switzerland
Sponsor: Computer Engineering Area Seminar
Time: 2:00 PM
Location: EE 118
Contact Name: Host: Prof. T.N. Vijaykumar
Technology forecasts indicate that device scaling will continue well
into the next  decade.   Unfortunately, it is becoming extremely
difficult to harness this increase in the number of transistors  into
performance due to a number of technological, circuit, architectural,
methodological and  programming challenges. In this talk, I will argue
that the key emerging show stopper is power.  Voltage scaling as a means
to maintain a constant power envelope with an increase in transistor 
numbers is hitting diminishing returns.  As such, to continue riding the
Moore's law we need to look  for drastic measures to cut power. This is
definitely the case for server chips in future datacenters,  where
abundant server parallelism, redundancy and 3D chip integration are
likely to remove  programming, reliability and bandwidth hurdles,
leaving power as the only true limiter.  I will present  results backing
this argument based on validated models for future server chips and
parameters  extracted from real commercial workloads. Then I use these
results to project future research  directions for datacenter hardware
and software.  


*BIO*

Babak Falsafi is a Professor in the School of Computer and Communication
Sciences at EPFL, and an  Adjunct Professor of Electrical and Computer
Engineering and Computer Science at Carnegie Mellon.  He is the
Microarchitecture thrust leader for the FCRP Center for Circuit and
System Solutions and  directs the Parallel Systems Architecture
Laboratory (PARSA) at EPFL. His research targets  architectural support
for parallel programming, resilient systems, architectures to break the
memory  wall, and analytic and simulation tools for computer system
performance evaluation. In 1999, in  collaboration with T. N. Vijaykumar
he showed for the first time that multiprocessors do not need  relaxed
memory consistency models to achieve high performance. He is a recipient
of an NSF CAREER  award in 2000, IBM Faculty Partnership Awards between
2001 and 2004, and an Alfred P. Sloan  Research Fellowship in 2004. He
is a senior member of IEEE and ACM.