Compilation and Optimization for High Performance Domain-Specific Computing

Event Date: May 13, 2010
Speaker: Dr. Deming Chen
Speaker Affiliation: Department of ECE
University of Illinois Urbana-Champaign
Sponsor: Prof Anand Raghunathan
Time: 1:30 PM
Location: EE 317
Contact Name: Prof A. Raghunathan
Contact Phone: (765) 494-3470
Contact Email:
As growing power dissipation and thermal effects disrupted the rising
clock frequency trend and threatened to annul Moore's law, the computing
industry has switched its route to higher performance through parallel
processing.  GPUs and FPGAs are becoming popular systems for speeding up
computation-intensive kernels of scientific, imaging and simulation
applications.  GPUs can execute hundreds of concurrent threads, while
FPGAs provide customized concurrency for highly parallel kernels. 
However, exploiting the parallelism available in these applications is
currently not a push-button task.  Often, the programmer has to expose
the application's fine and coarse grained parallelism by using special
programming languages.  CUDA is such a parallel language that is driven
by the GPU industry and is gaining significant popularity.

In the first half of my talk, I will introduce a new FPGA design flow
called FCUDA, which efficiently maps the coarse and fine grained
parallelism exposed in CUDA onto the reconfigurable fabric.  In the
second half of the talk, I will introduce circuit-level optimization for
timing speculation considering dynamic path behavior.  Traditional
circuit design focuses on optimizing the static critical paths no matter
how infrequently these paths are exercised dynamically.  Circuit
optimization is then tuned to the worst-case conditions to guarantee
error-free computation but may also lead to very inefficient designs.
 We propose a new circuit optimization technique "DynaTune" that
optimizes the most dynamically critical gates of a circuit and improves
the circuit's throughput under a fixed power budget. We test this
proposed technique with two timing speculation schemes - Telescopic Unit
and Razor Logic.


Dr. Deming Chen obtained his BS in computer science from University of
Pittsburgh, Pennsylvania in 1995, and his MS and PhD in computer science
from University of California at Los Angeles in 2001 and 2005
respectively.  He worked as a software engineer between 1995-1999 and
2001-2002.  He has been an assistant professor in the ECE department of
University of Illinois, Urbana-Champaign since 2005.  He is a research
assistant professor in the Coordinated Science Laboratory and an
affiliate assistant professor in the CS department.  His current
research interests include high-level synthesis, microarchitecture and
SoC design under parameter variation, FPGA synthesis and physical
design, and nano-systems design and nano-centric CAD techniques.  He is
a technical committee member for a series of conferences and symposia
and a TPC subcommittee or CAD track chair for several conferences.  He
is an associated editor for TVLSI, TCAS-I, JCSC, and JOLPE.  He obtained
the Achievement Award for Excellent Teamwork from Aplus Design
Technologies in 2001, the Arnold O. Beckman Research Award from UIUC in
2007, the NSF CAREER Award in 2008, the ASPDAC'09 Best Paper Award, and
the SASP'09 Best Paper Award.  He is included in the List of Teachers
Ranked as Excellent in 2008.