ECE 33700 - ASIC Design Laboratory

Note:

Formerly offered as ECE 495D - Spring 2002 through Fall 2005.

Course Details

Lecture Hours: 1 Lab Hours: 3 Credits: 2

Counts as:

  • EE Elective - Adv Level Lab
  • CMPE Core

Normally Offered:

Each Fall, Spring

Requisites:

ECE 27000 Minimum Grade of C

Catalog Description:

Introduction to standard cell design of VLSI digital circuits using VHDL hardware description language. Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis and testing.

Required Text(s):

None.

Recommended Text(s):

None.

Lab Outline:

Week(s) Activity
1 HDL synthesis and simulation design flow
2 Combinational logic design, coding styles, exhaustive test vectors
3 Lotic synthesis constraints, Assertions, directed test vectors, coverage
4 Sequential logic functions, HDL based state machine design, sequential tests

Engineering Design Content:

  • Establishment of Objectives and Criteria
  • Synthesis
  • Analysis
  • Testing
  • Evaluation

Engineering Design Consideration(s):

  • Economic
  • Manufacturability

Assessment Method:

Outcomes x through xv will be demonstrated by means of a final design project to be completed by teams of two or three students. Final projects will be evaluated on a per team basis, but individual participation will also be evaluated.