ECE 495A - Introduction to Design of Digital Computers

Lecture Hours: 3 Lab Hours: 3 Credits: 4

Counts as:

Experimental Course Offered: Fall 2000, Spring 2001, Fall 2001, Spring 2002, Fall 2002, Spring 2003

Catalog Description:
Computer design is the science and art of selecting and interconnecting hardware components to build a computer that meets functional, performance, and cost goals. In this course, students will learn to design a uniprocessor computer system, including processor datapath, processor control, memory systems, and I/O. The course provides a thorough and detailed treatment of basic computer arithmetic algorithms, multi-cycle implementations of modern computer instruction sets, pipelined CPU designs, design of cache hierarchy and virtual memory, and fundamentals of computer system I/O. The course also includes evaluation and analysis of processor and memory performance. A project which involves the design and implementation of multi-cycle CPU, and a pipelined CPU with a cache hierarchy using CAD tools is an integral part of the course.

Supplementary Information:
Web site: Course information, homework assignments, lab experiments, and reference documents are available on the course web site.

Nature of Design Experience

Through the combination of homework assignments and laboratory experiments, students will learn how to: (a) implement and instruction set with a multiple cycle non-pipelined architecture; (b) optimize and pipeline the CPU design; and (c) prototype variations of the CPU design using field programmable gate arrays (FPGAs) and measure their relative performance.

Required Text(s):
  1. Computer Organization and Design: The Hardware-Software Interface, 3rd Edition, J. L. Hennessy and D. A. Patterson, Morgan Kaufmann Publisher, 2002, ISBN No. 1558605967.

Recommended Text(s): None.

Learning Outcomes:

A student who successfully fulfills the course requirements will have demonstrated:
  1. an understanding of basic computer arithmetic algorithms. [a,c,e]
  2. an ability to understand and implement multi-cycle implementations of a computer instruction set. [a,c,e]
  3. an ability to understand and design a pipelined CPU, and cache hierarchy including virtual memory. [a,c,e]
  4. an understanding of the fundamentals of computer system I/O. [a,c,e]
  5. an ability to analyze and evaluate CPU and memory hierarchy performance. [a,b,e]
  6. experience with the design, simulation, and documentation of a multi-cycle CPU, and a pipelined CPU with a cache hierarchy using modern CAD tools. [a,b,c,e,g,i,k]

Lecture Outline:

Week Topic
1 Introduction, Performance
2 Cont., Instructions
3 Arithmetic
4 Cont., Datapath
5 Cont., Control
6 Cont.
7 Cont.
8 Pipelining
9 Cont.
10 Memory Hierarchies
11 Cont.
12 Cont.
13 More Arithmetic
14 Cont., I/O
15 Cont.
Final Final exam

Lab Outline:

Week Lab Exercises
1-2 VHDL/FPGA Review
3-10 Basic CPU Design, Simulation, and Prototyping
11-15 Extended CPU Design, Simulation, and Prototyping