ECE 59500 - Digital Logic SynthesisLecture Hours: 3 Credits: 3
Experimental Course Offered: Spring 2009
Logic Synthesis is the process of transforming a high-level circuit description into an optimized gate-level description. This course deals with the design of exact and heuristic algorithms for logic synthesis that form the basis for VLSI Computer-Aided Design (CAD) logic synthesis tools. Topics include synthesis of two-level circuits, synthesis of multi-level circuits, synthesis of finite-state machines and technology mapping.
Spring 2009 CRN 34119
- Logic Synthesis and Verification, G.D. Hachtel and F. Somenzi, Kluwer Academic Publishers, 2006, ISBN No. 978-0387310046.
- Logic Design Principles, E. J. McCluskey, Prentice Hall, 1996, ISBN No. 0-13-539784-7.
Learning Outcomes:A student who successfully fulfills the course requirements will have demonstrated:
- an ability to design minimal combinational logic circuits.. [a,c,k]
- an ability to design minimal finite-state machines.. [a,c,k]
|5||Two-Level Logic Synthesis; Boolean Algebras; Don't Care Conditions and Two-Level Logic; Selecting Prime Implicants; Heuristic Minimization|
|1||Binary Decision Diagrams|
|4||Finite-State Machine Synthesis; Minimization and Transversal of Finite-State Machines; Decomposition and Encoding; Retiming|
|1||Multi-Level Logic synthesis|
|1||Asynchronous Sequential Circuits|
Engineering Design Content:
Engineering Design Consideration(s):