ECE 49595 - ASIC Fabrication and Test II

Lecture Hours: 1 Lab Hours: 1 Credits: 2

Professional Attributes

Experimental Course Offered: Spring 2009, Spring 2010, Spring 2011

ECE 49500 (ASIC Fabrication and Test II) and Departmental Approval.

Catalog Description:
The second semester of a two-semester sequence to give teams of 3 to 6 students the experience of designing an ASIC, having the chip fabricated, and testing it. The team of students will develop requirements for a design, prepare the design using VHDL, Verilog, or schematic entry tools, create and use test benches to functionally verify the design, use automated tools to prepare a circuit layout, verify the final layout, submit the layout for fabrication, prepare a physical test bed, test or demonstrate the chip, and document all aspects of the design and test results.

Supplementary Information:
In the event that chip fabrication is unavailable, a reconfigurable logic based prototype may be tested instead. The instructor will meet weekly with each design team to monitor progress, explain new concepts, and guide the team in satisfying all course outcomes.

Required Text(s): None.

Recommended Text(s):
  1. VHDL for Logic Synthesis, 2nd Edition, Andrew Rushton, John Wiley & Sons, 1998, ISBN No. 047198325x.

Learning Objectives:

A student who successfully fulfills the course requirements will have demonstrated:
  1. Create testbenches and verify the functionality of the design in source code after logic synthesis and after layout. [e,k]
  2. Create an ASIC layout that is verified and ready for fabrication. [c,k]
  3. Design, implement, and use a hardware testbed for verification of functionality and performance of the chip after fabrication. Use a reconfigurable logic prototype for early testing and in lieu of a fabricated custom IC if necessary. [b,d,k]
  4. Communicate effectively by means of an oral presentation of the project either to students in another course or at a technical conference. [g]
  5. Communicate effectively in writing by means of a collective technical report on the project and individual reports on how each outcome was satisfied. [g]
Assessment Method for Learning Objectives: Any completed outcomes (1-7) will be assessed through evaluation of each students outcome completion report (described in outcome 8), corroborated by instructor observation during the semester, and by an end of semester interview. Outcome 8 will be assessed grading of the collective technical report and the individual outcome completion report.

Lab Outline:

Lab Activity
NOTE: Exact schedule is determined based on status of project at the end of the prior semester. It also depends on the schedule of the fabrication vendor. Week 1 will prepare complete ASIC layout (if not completed in semester1)
1 Verify functionality and manufacturability of the layout (if not completed in semester 1)
2 Submit design for Fabrication (if fabrication is possible)
3-12 Design and implement a hardware testbed
5-14 Test functionality and performance of ASIC and/or reconfigurable logic implementation
13-15 Prepare a testing report to be submitted to the organization that provided funds or wafer space for fabrication of the design (if fabrication is possible)
4-12 Prepare a paper and/or poster for submission to selected engineering education conference. If conference presentation isn't possible, give presentation to another ECE course.
13-15 Final Report
Final Exam Week. End of semester interview.

Engineering Design Content:


Engineering Design Consideration(s):