ECE 68800 - VLSI Testing and VerificationLecture Hours: 3 Credits: 3
Areas of Specialization(s):VLSI and Circuit Design
Normally Offered: Spring - odd years
ECE 55900 or consent of instructor
This course discusses different aspects of VLSI testing and formal verification of designs. Design and manufacturing defect models are introduced along with test generation and fault simulation algorithms targeting the different fault models. Both combinational and sequential logic testing are covered, and different synthesis for testability schemes such as BIST (Built-In-Self-Test), scan path design, etc. are introduced. Other new and emerging test and verification techniques are also discussed.
Required Text(s): None.
Recommended Text(s): None.
|2||Design Flow of VLSI Systems: (1) Design and manufacturing defect models (2) Simulation based design verification|
|3||Fault Simulation: (1) Parallel (2) Deductive (3) Concurrent|
|2||Functional Testing Methodologies: (1) Exhaustive testings (2) Pseudo-exhaustive testing|
|12||Structure Based Testing: (1) Fault model based testing: (A) Stuck-at faults; (B) Bridging faults; (C) Stuck-open faults; (D) Delay faults (2) Fault Grading (3) Automatic Test Pattern Generation Algorithms: (A) D-Algorithms; (B) PODEM; (C) FAN, etc.|
|2||Sequential Machine Testing: (1) Machine identification experiments (2) Modified PODEM and D-algorithms|
|6||Quiescent Current Testability Methods; deep submicron challenges|
|8||Design for Testability Methods: (1) Testable combinational/sequential circuits (2) Scan path design (3) Partial scan (4) Built-in Self Test (BIST) (5) Data compaction techniques|
|6||Introduction to Formal Design Verification|
|3||On-Line Testing Methods: (1) Self-checking circuits (2) Error detecting/correcting codes|