ECE 67000 - Modeling and Optimization of High-Performance Interconnects

Lecture Hours: 3 Credits: 3

Areas of Specialization(s):

VLSI and Circuit Design

Counts as:

Normally Offered: Fall - even years

Requisites:
ECE 55900 (or equivalent) or consent of instructor

Catalog Description:
RLC extraction of VLSI interconnects. Modeling of interconnects as RLC trees or networks. Elmore delay model. Reduced-order modeling: moment matching, Pade approximation, and Krylov-subspace methods. Device modeling with consideration of resistive shielding in the interconnection load. Delay calculation with consideration of devices and interconnects. Repeater insertion and planning at floorplanning. Timing-driven placement: zero-slack algorithm for delay budgeting, net-based placement, and path-based placement. High-performance clock synthesis: zero-skew routing, bounded-skew routing, and useful-skew routing. Term projects investigating interconnect-related issues are assigned.

Required Text(s): None.

Recommended Text(s):
  1. Circuits, Interconnections, and Packaging for VLSI, H.B. Bakoglu, Addison-Wesley, 1990, ISBN No. 0-201-06008-6.
  2. Interconnect Analysis and Synthesis, C.K. Cheng, J. Lillis, S Lin & N. Chang, John Wiley, 2000, ISBN No. 0-471-29366-0.
  3. Performance Optimization of VLSI Interconnect Layout, J. Cong, L. He, C.K. Koh, & P. H. Madden, in the VLSI Journal, 21, 1996..

Lecture Outline:

Lectures Major Topics
2 Introduction: trends of VLSI Interconnects, Challenges of Interconnect Design
6 Extraction of RLC Parasitics
3 RLC Simulation
2 Elmore Delay Model
7 Reduced Order Modeling
2 Driver Modeling and Delay Calculation
6 Repeater Insertion and Planning
6 Timing-Driven Placement
6 High-Performance Routing
1 Mid-term Exam
3 Term Project Presentation