ECE 495G - ASIC Fabrication and Test I

Credits: 2

This is an experiential learning course.

Counts as:

Experimental Course Offered: Fall 2007

Catalog Description:
The first semester of a two-semester sequence to give teams of 3 to 6 students the experience of designing an ASIC, having the chip fabricated, and testing it. The team of students will develop requirements for a design, prepare the design using VHDL, Verilog, or schematic entry tools, create and use test benches to functionally verify the design, use automated tools to prepare a physical test bed, test or demonstrate the chip, and document all aspects of the design and test results. In the event that chip fabrication is unavailable, a reconfigurable logic based prototype may be tested instead. The instructor will meet weekly with each design team to monitor progress, explain new concepts, and guide the team in satisfying all course outcomes.

Supplementary Information:
Outcomes 1,2,3, and 9 must be demonstrated during ASIC FABRICATION AND TEST I by every team member. Each Other outcomes may be demonstrated, but are not required until ASIC FABRICATION AND TEST II. Engineering Design Content: requirements definition, synthesis of a circuit architecture to meet requirements, design of functional verification tests, analysis of circuit performance, use of advanced design and analysis software. Engineering Design Considerations: Economic: make trade-offs between performance, features, and circuit area. Manufacturability: ensure that ASIC design satisfies requirements for fabrication and is designed in a way to facilitate testing of the fabricated design.

Required Text(s): None.

Recommended Text(s):
  1. Digital Integrated Circuits, 2 Edition, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Prentice-Hall, 2003, ISBN No. 0-13-090996-3.
  2. VHDL for Logic Synthesis, 2 Edition, Andrew Rushton, John Wiley & Sons, 1998, ISBN No. 0-471-98325-X.

Learning Outcomes:

  1. Explain critical steps in the preparation of an ASIC design for fabrication and the tools required to perform these steps: functional verification, logic synthesis, physical layout, physical verification, and timing verification. (ALL Individually). [None]
  2. Use advanced ASIC design software for: functional verification, logic synthesis, physical layout, physical verification, and timing verification. Create or use scripts to automate repetitive aspects of the process. (Each student must participate in some aspect of this). [None]
  3. Define functional and physical requirements for an ASIC design of the team's choosing. (Each student must participate in some aspect of this). [None]
  4. Define a circuit architecture that can be expected to meet functional requirements subject to performance and area constraints. (At least one student). [None]
  5. Estimate speed, throughput, and expected circuit area to ensure that constraints are satisfied. (At least one student). [None]
  6. Create testbenches and verify the functionality of the design in source code, after logic synthesis, and after layout. (At least one student). [None]
  7. Create an ASIC layout that is verified and ready for fabrication (At least one student). [None]
  8. Design, implement, and use a hardware testbed for verification of the chip after fabrication. If fabrication is not available, create a reconfigurable logic prototype for testing. Off-the-shelf components may be used. The testbed should verify functionality and performance. (Each student must participate in some aspect of this).. [None]
  9. Communicate effectively in writing by means of a collective technical report on the project and individual reports on how each outcome was satisfied. (Each student must participate in some aspect of this). [None]

Lecture Outline:

Semester 1: Design
Define Requirements and Constraints
Define Architecture
Prepare design using a hardware description language
Synthesize design to gate level representation
Prepare Simulation Test Benches
Verify functionality of source code and gate level design
Prepare ASIC Layout. Might not complete until second semester.
Verify functionality and manufacturability of the layout. Might not complete until second semester.
Submit design for Fabrication (if fabrication is available)
The exact sequence and semester breakdown will vary depending on the project. In some cases, students will be testing ASIC designs created by a previous team.

Engineering Design Content:

Synthesis
Analysis
Construction
Testing

Engineering Design Consideration(s):

Economic
Manufacturability