Skip navigation

ECE 27000 - Introduction to Digital System Design

Lecture Hours: 3 Lab Hours: 3 Credits: 4

Professional Attributes
EE Core

Normally Offered: Each Fall, Spring

ECE 20100 [may be taken concurrently]

Catalog Description:
An introduction to digital system design, with an emphasis on practical design techniques and circuit implementation.

Required Text(s):
  1. Digital Design Principles and Practices, 5th Edition, John Wakerly, Pearson Publication, 2018, ISBN No. 978-0134460093.

Recommended Text(s): None.

Learning Objectives:

A student who successfully fulfills the course requirements will have demonstrated:
  1. an ability to analyze and design CMOS logic gates. [a,e,k]
  2. an ability to analyze and design combinational logic circuits. [a,e,k]
  3. an ability to analyze and design sequential logic circuits. [a,e,k]
  4. an ability to analyze and design computer logic circuits. [a,e,k]
  5. an ability to realize, test, and debug practical digital circuits. [b,c,k]
Assessment Method for Learning Objectives: Students must demonstrate basic competency in all the outcomes, listed above, in order to receive a passing grade for the course. Basic competency will be assessed based on a specific set of exam questions, for which a minimum score of [(exam mean) - (standard deviation (limited to the range of 40% to 60%) will be required. Two opportunities will be provided to demonstrate competency in these outcomes: (1) the Primary Assessment Exams; and (2) the Comprehensive Final Assessment exam. Two opportunities will also be provided to demonstrate competency in Outcome 5: earning a minimum score of 60% on each experiment or a minimum score of 60% on the Lab Practical Exam. A score greater than or equal to the passing threshold on either of these assessments will be sufficient to establish basic competency.

Lecture Outline:

Week(s) Lecture Topics
3.5 Module 1: Switching Algebra and CMOS Logic Gates. Number systems, base conversion, switching algebra, basic electronic components and concepts, logic signals, CMOS logic circuits, logic levels and noise margins, current sourcing and sinking, transition time, propagation delay, power consumption and decoupling, Schmitt triggers, transmission gates, three-state and open-drain outputs.
3 Module 2: Combinational Logic Circuits. Combinational circuit analysis and synthesis, mapping and minimization, timing hazards, XOR/XNOR functions, programmable logic devices, Verilog hardware description language, combinational building blocks: decoders, encoders, and multiplexers.
3 Module 3: Sequential Logic Circuits. Bi-stable elements, set-reset and data latches, data and toggle flip-flops, state machine structure and analysis, clocked synchronous state machine synthesis, state machine design examples: sequence generators, counters and shift registers, and sequence recognizers.
3.5 Module 4: Arithmetic and Computer Logic Circuits. Signed number notation; radix addition and subtraction; adder, subtractor, and comparator circuits; carry look-ahead adder circuits; multiplier circuits; BCD adder circuits; simple computer top-down specification, instruction execution tracing, bottom-up realization, basic extensions, and advanced extensions.
2 Hourly exams and review sessions

Lab Outline:

Week(s) Activity
1 Breadboard Techniques and Logic Function Demonstration
2 Measurement of Gate Electrical and Timing Characteristics
3 Implementation of Dual and Complement Functions
4 Investigation of Open-Drain Gate Characteristics
5 Investigation of Timing Hazards
6 Introduction to ispLEVER and PLDs
7 7-segment Display PLD Exercises
8 Introduction to Sequential Circuits
9 Introduction to ispMACH 4256ZE Development Board
10 Scrolling 7-Segment LED Display
11 Digital Combination Lock with Pseudo-Random Combination
12 The "Academic Exercise" Game - or - The Radix Price is Right!
13 The Raulmatic 716 Simpler Computer
14 Lab Practical Exam

Engineering Design Content: