ECE 495D - ASIC Design Laboratory
Course Details
Lecture Hours: 1 Lab Hours: 3 Credits: 2
Counts as:
Experimental Course Offered:
Spring 2006
Catalog Description:
Catalog Description:
Introduction to the principles and practices of computer engineering, ranging from basic logic to the design of high-end computing hardware and software. This course covers numerical representations, digital logic design, low-level and high-level programming, and program design for modern multicore processors (such as the Core Duo used in many desktop and server machines or the Cell-BE used in the Playstation 3).
Credit cannot be obtained for both ECE 495K and CS 159 or equivalent.
Required Text(s):
- VHDL for Logic Synthesis , 2rd Edition , Andrew Rushton , Wiley , ISBN No. 0-471-98325-X
Recommended Text(s):
None.
Learning Outcomes:
- understand and use major syntactic elements of VDHL - entities, architectures, processes, functions, common concurrent statements, and common sequential statements. [a,k]
- design common sequential functions: flip-flops, registers, latches, and state-machines. [a,c,k]
- create a VDHL test bench and use it to test/verify a sequential VHDL design of moderate complexity. [b,k]
- place, route, and verify timing of a standard cell design. [b,c,k]
- draw, given commented VHDL code of moderate complexity, a corresponding RTL level block diagram. [a,b,k]
- use, modify, and create scripts to control the synthesis process. [k]
- use different design styles, constraints, and optimization options to achieve required synthesis results. [a,c,e,k]
- explain the difference between various ASIC design approaches - standard cell, full custom, and programmable devices. [a]
- prepare functional and interface requirements for a sequential design project of the student's choosing. [a,c,e]
- create the hierarchical decomposition of a sequential design. [a,c,e]
- gain experience in the oral presentation of their work to others. [g]
- work in a team and negotiate the division of labor. [d]
- gain familiarity with the use and purpose of design reviews. [g]
- prepare final design documentation sufficient for another engineer to use, test, or enhance the design. [g]
Lab Outline:
Week(s) | Topic(s) |
---|---|
1 | Course overview, VHDL synthesis and simulation design flow |
2 | Combinational logic design - schematic and VHDL |
3 | Use of test benches, timing constraints, optimization trade-offs |
4 | Sequential logic functions in VHDL |
5 | State machine design in VHDL |
6-7 | System level design in VHDL; Writing ASIC specifications |
8-9 | ASIC Place and Route; Timing closure |
10-11 | Advanced VHDL topics |
12-13 | ASIC and programmable logic implementation technologies (full custom, standard cell, FPGA) |
14-15 | Current VLSI topics |
Final | Student presentations and final reports |
Engineering Design Content:
- Establishment of Objectives and Criteria
- Synthesis
- Analysis
- Testing
- Evaluation
Engineering Design Consideration(s):
- Economic
- Manufacturability
Assessment Method:
Outcomes x. through xv. Will be demonstrated by means of a final design project to be completed by teams of two or three students. Final projects will be evaluated on a per team basis, but individual participation will also be evaluated.