ECE 595Z - Digital Logic Synthesis
Course Details
Lecture Hours: 3 Credits: 3
This is an experiential learning course.
Counts as:
Experimental Course Offered:
Fall 2003, Fall 2004
Catalog Description:
Logic synthesis is the process of transforming a high-level circuit description into an optimized gate-level description. This course deals with the design of exact and heuristic algorithms for logic synthesis that form the basis for VLSI Computer-Aided Design (CAD) logic synthesis tools. Topics include synthesis of two-level circuits, synthesis of multi-level circuits, synthesis of finite-state machines and technology mapping.
Course Objectives:
Provide the basic knowledge necessary for the design and understanding of VLSI CAD logic synthesis tools for two-level synthesis, multi-level synthesis, finite-state machine synthesis and technology mapping.
Required Text(s):
- Logic Synthesis and Verification Algorithms , G.D. Hachtel and F. Somenzi , Kluwer Academic Publishers , 1996 , ISBN No. 0-7923-9746-0
Recommended Text(s):
- Logic Design Principles , E.J. McCluskey , Prentice-Hall , 1986 , ISBN No. 0-13-539784-7
Learning Outcomes:
- An ability to design minimal combinational logic circuits. [a,c,k]
- An ability to design minimal finite-state machines. [a,c,k]
Lecture Outline:
Week(s) | Lecture Topics |
---|---|
5 | Two-Level Logic Synthesis Boolean Algebras, Don't Care Conditions and Two-Level Logic, Selecting Prime Implicants, Heuristic Minimization |
1 | Special Functions |
1 | Binary Decision Diagrams |
4 | Finite-State Machine Synthesis Minimization and Traversal of Finite-State Machines, Synthesis of Finite-State Machines, Decomposition and Encoding, Retiming |
1 | Multilevel Logic Synthesis |
1 | Technology Mapping |
1 | Asynchronous Sequential Circuits |
Engineering Design Content:
- Synthesis
- Analysis
Engineering Design Consideration(s):
- Economic
- Manufacturability
Assessment Method:
The first midterm exam and half of the questions on the final exam will measure outcome i). A student who fails both the first midterm exam and the corresponding half of the final exam will fail the course. The second midterm exam and half of the questions on the final exam will measure outcome ii). A student who fails both the second midterm exam and the corresponding half of the final exam will fail the course.