Note:

May be used as a Computer Engineering Elective or an Electrical Engineering Elective upon completion of both ASIC FABRICATION AND TEST I and ASIC FABRICATION AND TEST II.

Counts as:

Experimental Course Offered:

Fall 2006

Catalog Description:

The first semester of a two-semester sequence to give teams of 3 to 6 students the experience of designing an ASIC, having the chip fabricated, and testing it. The team of students will develop requirements for a design, prepare the design using VHDL, Verilog, or schematic entry tools, create and use test benches to functionally verify the design, use automated tools to prepare a circuit layout, verify the final layout, submit the layout for fabrication, prepare a physical test bed, test or demonstrate the chip, and document all aspects of the design and test results. In the event that chip fabrication is unavailable, a reconfigurable logic based prototype may be tested instead. The instructor will meet weekly with each design team to monitor progress, explain new concepts, and guide the team in satisfying all course outcomes.

Learning Outcomes:

1. Explain critical steps in the preparation of an ASIC design for fabrication and the tools required to perform these steps: functional verification, logic synthesis, physical layout, physical verification, and timing verification. (All Individually). [None]
2. Use an advanced ASIC design software for: functional verification, logic synthesis, physical layout, physical verification, and timing verification. Create or use scripts to automate repetitive aspects of the process. (Each student must participate in some aspect of this). [None]
3. Define functional and physical requirements for an ASIC design of the teams choosing. (Each student must participate in some aspect of this). [None]
4. Define a circuit architecture that can be expected meet functional requirements subject to performance and area constraints. (At least one student). [None]
5. Estimate speed, throughput, and expected circuit area to ensure that constraints are satisfied. (At least one student). [None]
6. Create test benches and verify the functionality of the design in source code, after logic synthesis, and after layout. (At least one student). [None]
7. Create an ASIC layout that is verified and ready for fabrication. (At least one student). [None]
8. Design, implement, and use a hardware test bed for verification of the chip after fabrication. If fabrication is not available, create a reconfigurable logic prototype for testing. Off-the-shelf components may be used. The test bed should verify functionality and performance.. (Each student must participate in some aspect of this). [None]
9. Communicate effectively in writing by means of a collective technical report on the project and individual reports on how each outcome was satisfied. (Each student must participate in some aspect of this). [None]

Lecture Outline:

Assessment Method:

Any completed outcomes (1-7) will be assessed through evaluation of each students outcome completion report (described in outcome 8), corroborated by instructor observation during the semester, and by an end of semester interview. Outcome 8 will be assessed grading of the collective technical report and the individual outcome completion report.