April 8, 2015
Job Opening at Intel
Position Type: | Research |
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Priority: | No |
Degree Requirement: | PhD, Post Doctorate |
I am looking for full time candidates for my team to play the role of verification engineer who can work on development and maintenance of a functional model of a memory controller.
A little bit info about my team:
MIPL (Memory IP Logic team) at Intel works on development and verification of memory PHY* from cradle to Grave. Our team is located in Folsom,CA and works on architecture,design,layout and all other parts of the design cycle so you can think of us as a standalone team who delivers a hard IP to SoC teams.
*Memory PHY is a physical layer (IO buffer) mixed signal design that sits between the memory controller and the DRAM memory and is responsible for taking care of converting digital signals from memory controller to Analog signals that can be read by the DRAM (very crude definition).
The functional model is used to validate PHY before delivering it to SoC teams.
Preferred candidates should:
Have a strong background in SystemVerilog.
Be able to understand protocol specs.
Be able to work on their own with minimal hand holding.
Have strong background in Object Oriented Programming.
Scripting Knowledge and/or OVM/UVM will be a plus.
Graduate students preferred but exceptions can be made for undergraduates with strong background in verification.
Graduating in May 2015.
If you or anyone you know who may be interested in the job opening then please send me your/their resume.
Prashant Lalwani