Task 016/017: End-to-End Performance Benchmark / Neuromorphic Design Flow

ABSTRACT: Multi-domain ferroelectric transistors (FeFETs) are amongst the most promising device technologies for synaptic design by virtue of their compact bit-cell, electric-field driven programming and the possibilities of multi-level storage. In this work, we design and evaluate FeFET-based synaptic arrays supporting signed and unsigned weights of different precisions. We propose a new design which support in-situ multiply-and-accumulate (MAC) operations with signed inputs and signed weights in the quinary regime. To achieve multiple and programmable precision of the inputs and with an objective to enhance parallelism of MAC operations under sense margin constraints, we employ multi-pulse encoding scheme. We show that the proposed design featuring in-situ signed MAC operation leads to 47% higher energy efficiency compared to the standard synapse design and is most beneficial for ultra-low precision (<=5 levels) neural networks. Our results show that FeFET based computing-in-memory shows 4.5X energy savings compared to the standard FeFETs with near-memory MAC operations. We have also analyzed the impact of the unique features of the FeFET synapses on the accuracy of RESNET20 architecture. Through extensive simulations, we co-explore FE thickness, crossbar size, bit slices and array configurations and the effect on circuit level non-idealities and application level accuracy. Our results show that the inherent non-linearity in the FeFETs can be beneficial for improving the accuracy. Furthermore, our analysis establishes the dependence on system accuracy on FE thickness and suggests that the optimal value of FE thickness to maximize accuracy is around 7nm. 

 

BIO: Chunguang Wang is a PhD student at Purdue ECE since Fall 2018 and he is advised by Prof. Sumeet Gupta. Prior to this, he completed his MSc and BSc in microelectronics from Peking University, Beijing, China in 2018 and 2015, respectively. His current research focus is on in-memory computing based on FeFETs.