Task 007: Distributed Learning and Inference

Event Date: May 28, 2020
Time: 2:00 p.m. (ET) / 11:00 a.m. (PST)
Priority: No
School or Program: Electrical and Computer Engineering
College Calendar: Show
Ikenna Okafor, The Pennsylvania State University
Bandwidth Efficient Architecture for Deep Neural Networks
Current studies show that traffic between the Convolutional Neural Network (CNN) accelerators and off-chip memory requires considerable power consumption as researchers build deeper networks in order to improve detection accuracy. This is especially critical for low power embedded devices. Since on-chip data movement costs less in terms of power consumption, significant savings can be obtained by caching and reusing timely data between adjacent layers, rather than transfer it off chip. Moreover, taking advantage of specific layer sequences can further lessen output memory bandwidth pressure. However, the order of computation within a layer must be orchestrated properly to ensure efficiency.  In this work, we propose an on-chip accelerator architecture which allows reusing timely data and significantly reduces feature map movement between an accelerator and off-chip memory, during computation.
Ikenna Okafor is a computer science and engineering PhD student at The Pennsylvania State University. He completed his Bachelors of science in computer engineering at The Pennsylvania State University. His Masters of Science in computer science and engineering was also completed at The Pennsylvania State University which dove into Hardware acceleration for Visual object search. Currently Ikenna's research interest are in computer architecture and machine learning with a focus on utilizing machine learning for smart hardware accelerators and resource management.