Task 007: Distributed Learning and Inference
|Event Date:||September 19, 2019|
|Time:||2:00pm ET/ 11:00am PT
|School or Program:||Electrical and Computer Engineering
Nagadastagiri Challapalle, Pennsylvania State University Adaptive Neural Network Architectures for Power Aware Inference
As an increasingly diverse array of edge devices become platforms for neural networks, the power and compute limitations of these platforms become key design constraints, often imposing trade-offs among performance, accuracy, and power/energy requirements for inference tasks. Moreover, in edge deployment scenarios, dynamic variability in both the power and computation capabilities of these platforms is an equally important driver of design decisions in matching a neural network model with a given end device and deployment scenario. In this work we propose a novel method for adaptive neural network architectures to boost performance as power becomes available without necessitating a complete reconfiguration of model parameters. We show that, due to the stochastic nature of neural networks, models can be constructed with enough independence to be effectively ensembled while sharing a common convolutional base. This allows for a trade-off between power consumption and model accuracy without redeploying an entirely new model. Our method is agnostic to the base network and can be added to existing networks with minimal retraining. We find this approach particularly well suited for IoT devices and distributed autonomous applications where available power and compute resources are time varying.
Naga Challapalle received the M.Tech degree from Indian Institute of Technology Kanpur, in 2016. Currently, he is pursuing PhD degree in Computer Science and Engineering in Pennsylvania State University under Dr. Vijaykrishnan Narayanan since 2018. His primary research interest are software-hardware codesign for data and compute intensive application such as AI, Graph Analytics using emerging technologies. Prior to Joining PhD, he worked as Hardware Engineer in Microarchitecture Research Labs, Intel Labs, Bangalore for 2 years.