Task 005/006: Fundamental Limits on Energy-Accuracy Trade-offs of In-memory Architectures
|Event Date:||November 21, 2019|
|Time:||2:00pm ET/ 11:00am PT
Sujan Gonugondla, University of Illinois at Urbana-Champaign Fundamental Limits on Energy-Accuracy Trade-offs of In-memory Architectures
In-memory architectures have drawn much interest due to their ability to reduce the energy and latency cost of memory accesses for machine learning applications. While in-memory architectures have shown remarkable gains in decision-making EDP of > 100× over an equivalent von Neumann architecture with minimal/no loss in inference accuracy, it is not clear that these gains are sustainable for larger problem sizes across data sets and inference tasks. Unlike digital architectures, where quantization noise is the sole contributor to the output SNR, in-memory architectures need to contend with both quantization noise as well as analog non-idealities caused by process, temperature, and voltage (PVT) variations raising the question:
What are the fundamental limits on the energy-delay-accuracy trade-off in In-memory architectures?
Answering this question is made challenging due to the rich design space occupied by in-memory architectures encompassing a huge diversity of available memory devices, bitcell circuit topologies, and architectural options. To address this question, we propose a compositional framework for in-memory architectures implementing the vector dot-product (DP) computation in matrix-vector multiplication (MVM) ubiquitous in inference algorithms. This framework allows one to ‘explain’ the construction of existing in-memory architectures and enables the construction of an SNR analysis methodology that can be employed to comprehend the achievable accuracy of various in-memory architectures. This talk will describe this framework and demonstrate its use in obtaining the fundamental limits on energy-delay-accuracy of in-memory architectures for inference workloads.
Sujan Gonugondla received the Bachelors and Masters in Technology degrees in Electrical Engineering from the Indian Institute of Technology Madras, Chennai, India, in 2014. He is currently pursuing the Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign, Champaign, IL, USA. His current research interests are in energy-efficient integrated circuits for machine learning systems and low complexity algorithms for inference under resource constraints.
He had been a recipient of the Dr. Ok Kyun Kim Fellowship 2018-19 and the M. E. Van Valkenburg Graduate Research award 2019-20 from the ECE department at the University of Illinois at Urbana-Champaign, and the ADI Outstanding Student Designer Award 2018. He has received Best Student Paper awards in International Conference on Acoustics, Speech and Signal Processing in 2016 and International conference in Circuits and Systems in 2018.