Task 004: Neural Primitives
|Event Date:||October 14, 2021|
|Time:||11:00 am (ET) / 8:00am (PT)
Gokul Krishnan, Arizona State University SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks
In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect multiple small chips (i.e., chiplets) to form a large computing system, presenting a feasible solution beyond a monolithic IMC architecture to accelerate large deep learning models. This paper presents a new benchmarking simulator, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore the potential of such a paradigm shift in IMC architecture design. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to realize an end-to-end system. SIAM is scalable in its support of a wide range of deep neural networks (DNNs), customizable to various network structures and configurations, and capable of efficient design space exploration. We demonstrate the flexibility, scalability, and simulation speed of SIAM by benchmarking different state-of-the-art DNNs with CIFAR-10, CIFAR-100, and ImageNet datasets. We further calibrate the simulation results with a published silicon result, SIMBA. The chiplet-based IMC architecture obtained through SIAM shows 130× and 72× improvement in energy-efficiency for ResNet-50 on the ImageNet dataset compared to Nvidia V100 and T4 GPUs.
Gokul Krishnan received his Bachelors degree in Electronics and Communication Engineering from Govt. Model Engineering College, Kochi, India in 2016. He is currently working towards a Ph.D. degree in Electrical Engineering at Arizona State University, Tempe, AZ, USA. His current research interests include neuromorphic hardware and FPGA design for deep learning, joint algorithm-architecture design for learning on-a-chip, model compression of DNNs, microarchitecture design, and performance modeling for CMOS and post-CMOS-based hardware architectures. He is the recipient of the Joseph A. Barkson Fellowship for 2020-21 and the GPSA Outstanding research award for 2021.