Task 003: Algorithms for Emerging Hardware

ABSTRACT: In-memory computing (IMC) architectures exhibit an intrinsic trade-off between computational accuracy and energy efficiency. eNVM-based IMCs are compute SNR limited and this limits their achievable energy efficiency and compute density. As a result, eNVM-based IMCs lag significantly behind both SRAM-based IMCs and digital accelerators in terms of both energy efficiency and compute density. A key reason for this limitation is the need for high-sensitivity readout circuitry required to accurately sense small changes in small resistances in the presence of analog non-idealities. 

 

This talk will present an analytical approach to determine the fundamental limits on the compute SNR of MRAM-, ReRAM-, and FeFET-based crossbars. The impact of dot-product dimension, input impedance of sensing circuitry, and device resistive contrast on the maximum achievable bank-level compute SNR is studied in order to obtain SNR-optimal design parameters. Finally, by mapping a ResNet- 20 (CIFAR-10) network onto the three types of resistive crossbars, it is shown that the bank-level compute SNR-optimal design parameters maximizes network-level accuracy thereby providing a local accuracy metric for IMC designers to optimize. 

 

BIO: Saion Kumar Roy received the B.Tech. and M.Tech. degrees in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, India, in 2018. Since 2018, he has been conducting his doctoral studies under Professor Naresh Shanbhag’s supervision at the University of Illinois at Urbana-Champaign. His research interests include energy-efficient integrated circuit design with focus on SRAM and eNVM-based in-memory computing.