C-BRIC JUMP e-Workshop

Abstract

As machine learning (ML) pervades the spectrum of computing devices, there is growing interest in TinyML, or bringing ML to the Billions of tiny devices that are deeply embedded into the fabric of our lives. These devices, which are typically powered by microcontroller-class processors, are extremely power, cost and size constrained, often precluding the use of accelerators with large arrays of processing elements and large on-chip memories. For such platforms, improving the efficiency of ML workloads on general-purpose processors is a key challenge. We present an overview of our work that improves the efficiency of TinyML systems by exploiting key characteristics of the workloads. First, we discuss Sparsity aware Core Extensions (SparCE), a set of micro-architectural and ISA extensions that leverage sparsity in data structures by dynamically detecting and skipping redundant instructions even before they are fetched. Second, we present Value Similarity Extensions (VSX), which detect instruction sequences that will produce similar results to recently executed instructions and skip the entire fetch-decode-execute process for these sequences to improve performance. Our evaluations suggest that these lightweight hardware enhancements can improve the speed and energy of ML workloads by upto 4X with minimal (1-2%) area and power overheads.

 

Bio

Anand Raghunathan received the B. Tech. degree in Electrical and Electronics Engineering from the Indian Institute of Technology, Madras, India, and the M.A. and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, NJ.

 

Dr. Raghunathan is currently a Silicon Valley Professor in the School of Electrical and Computer Engineering at Purdue University and the Associate Director of the Center for Brain-Inspired Computing (C-BRIC), and directs research in the Integrated Systems Laboratory in the areas of System-on-chip and Embedded System Design, Domain-specific computing, and Heterogeneous parallel computing. Previously, he was a Senior Research Staff Member at NEC Laboratories America in Princeton, NJ, where he led research projects related to System-on-Chip architectures, design methodologies, and design tools. He has co-authored a book (``High-level Power Analysis and Optimization'') and eight book chapters, and has presented several full-day and embedded conference tutorials in the above areas. He holds 20 U.S patents and has authored over 200 refereed conference and journal publications. He has received eight best paper awards at leading conferences - ACM/IEEE Design Automation Conference (1999 and 2000), ACM/IEEE International Conference on HW/SW Codesign and System Synthesis (2006), IEEE International Conference on VLSI Design (one in 1998 and two in 2003), IEEE International Conference on Cloud Computing (2010), and ACM/IEEE International Symposium on Low Power Electronics and Design (2012) - and four best paper award nominations at the ACM/IEEE Design Automation Conference (1996, 1997, 2003, and 2012). He received a Patent of the Year Award (an award recognizing the invention that has achieved the highest impact), and two Technology Commercialization Award from NEC. He was chosen by MIT's Technology Review among the TR35 (top 35 innovators under 35 years, across various disciplines of science and technology) in 2006, for his work on "making mobile secure".

 

Dr. Raghunathan has been a member of the technical program and organizing committees of several leading conferences and workshops. He has served as Program Co-chair for the ACM/IEEE International Symposium on Low Power Electronics and Design, the ACM/IEEE International Conferences on Compilers, Architecture and Synthesis for Embedded Systmes, the IEEE VLSI Test Symposium and the IEEE International Conference on VLSI Design. He has served as Associate Editor of the IEEE Transactions on CAD, the IEEE Transactions on VLSI Systems, ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on Mobile Computing, ACM Transactions on Embedded Computing Systems, IEEE Design & Test of Computers, and the Journal of Low Power Electronics. He was a recepient of the IEEE Meritorious Service Award (2001) and Outstanding Service Award (2004). He is a Fellow of the IEEE and was elected a Golden Core Member of the IEEE Computer Society in 2001, in recognition of his contributions.