Vijay Narayanan is a Distinguished Professor of Computer Science & Engineering and Electrical Engineering at the Pennsylvania State University. Vijay received his Bachelors in Computer Science & Engineering from University of Madras, India in 1993 and his Ph.D. in Computer Science & Engineering from the University of South Florida, USA, in 1998. He is a co-director of the Microsystems Design Lab. His research and teaching interests are in Power Aware Computing, Computer Architecture Embedded Systems, Design and Design Automation of Electronic Systems. He is a fellow of ACM and IEEE and leads the Architecture, Benchmarking and Circuits Thrust in the DARPA/SRC LEAST Center, through which he works with device experts in designing new circuits and system using emerging devices.
- K. Swaminathan, E. Kultursay, V. Saripalli, V. Narayanan, M. T. Kandemir, S. Datta. Steep-Slope Devices: From Dark to Dim Silicon. IEEE Micro 33(5): 50-59 (2013)
- H. Liu, S. Datta, V. Narayanan: Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications. ISLPED 2013: 145-150, September 2013
- V. Narayanan, S. Datta, G. Cauwenberghs, D. M. Chiarulli, S. P. Levitan, P. Wong. Video analytics using beyond CMOS devices. DATE 2014: 1-5
- K. Ma, Zheng, Y., Li, S., Swaminathan, K., Li, X., Liu, Y., Sampson, J., Xie, Y., & Narayanan, V. (2015). Architecture exploration for ambient energy harvesting nonvolatile processors. 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA. (pp. 526–537). Best Paper Award
- M. J. Cotter, Y. Fang, S. P. Levitan, D. M. Chiarulli, V. Narayanan. Computational Architectures Based on Coupled Oscillators. ISVLSI 2014: 130-135
- J. P. Sustersic, B. Wyble, S. Advani, V. Narayanan. Towards a unified multiresolution vision model for autonomous ground robots. Robotics and Autonomous Systems 75: 221-232 (2016).
- V. Saripalli, S. Datta, and V. Narayanan. August 2008. Ultra Low Power Signal Processing Architectures enabling Next-Generation BioSensing and Biomimetic System. Proceedings of the IEEE Biomedical Circuits and Systems Conference.
- D. Duarte, Narayanan Vijaykrishnan, M. J. Irwin. December 2002. A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations. IEEE Transactions on VLSI, 10(6):844-855. IEEE Circuit and Systems Transactions on VLSI Best Paper Award
- H. Moon, K. Irick, V. Narayanan, R. Sharma, N. Jung. April 24, 2012, Apparatus and method for measuring audience data from image stream using dynamically-configurable hardware architecture, US Patent 8165386.
- N. Shukla, A. Parihar, M. Cotter, M. Barth, X. Li, N. Chandramoorthy, D. G. Schlom, V. Narayanan, A. Raychowdhury and S. Datta, "Pairwise coupled hybrid vanadium dioxide-MOSFET (HVFET) oscillators for non-boolean associative computing," Proceedings of the IEEE International Electron Devices Meeting (IEDM 2014).