Dan Hammerstrom

Dan Hammerstrom

Dr. Hammerstrom is a Professor in the Electrical and Computer Engineering Department at Portland State, and holds a joint appointment in the IDE (Information, Computation, and Electronics) Department at Halmstad University, Halmstad, Sweden. He is a Life Fellow of the Institute of Electrical and Electronic Engineers (IEEE) and has been an Editor for the IEEE Transactions on Nanotechnology, an Associate Editor for the IEEE Transactions on Neural Networks, the Journal of the International Neural Network Society (INNS), and the International Journal of Neural Networks. He has authored over seventy research papers and eight book chapters, and holds seven patents. Dr. Hammerstrom has been a Visiting Scientist at the Royal Institute of Technology in Stockholm, Sweden and the NASA Ames Research Center in Mountain View California.

  1. "Coupled-Oscillator Associative Memory Array Operation for Pattern Recognition," D. Nkonov, G. Csaba, W. Porod, T. Shibata, D. Voils, D. Hammerstrom, I. Young, and G. Bourianoff, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 1, pp. 85-93, 2015.
  2. "Performance/price Estimates for Cortex-Scale Hardware: A Design Space Exploration," Mazad S. Zaveri and Dan Hammerstrom, Neural Networks, 2011, 24(3): 291-304.
  3. "Nano/CMOS implementations of Inference in Bayesian Memory – An Architecture Assessment Methodology," Mazad S. Zaveri and Dan Hammerstrom, IEEE Transactions on Nanotechnology, Vol. 9, No. 2, March 2010, pp. 194-211.
  4. "Cortical Models onto CMOL and CMOS – Architectures and Performance/price," Changjian Gao and Dan Hammerstrom, IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 54, No. 11, pp. 2502-2515, November 2007.
  5. "Architectures for Silicon Nanoelectronics and Beyond," Iris Bahar, Justin Harlow, Dan Hammerstrom, William Joyner, Clifford Lau, Diana Marculescu, Alex Orailoglu, and Massoud Pedram, IEEE Computer, January 2007
  6. "Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic based Reconfigurable Architecture", Kamela C. Rahman, Dan Hammerstrom, Yiwei Li, Hongyan Castagnaro, and Marek A. Perkowski. IEEE Transactions on Nano-technology, Volume: 15, Issue: 4, July 2016.
  7. "Comparing SFMD and SPMD Computation for On-Chip Multiprocessing of Intermediate Level Image Understanding Algorithms," Steve Rehfuss and Dan Hammerstrom, Proceedings of the conference for Computer Architectures for Machine Perception 1997, Boston MA, October 1997.
  8. "Image Processing Using One-Dimensional Processor Arrays," Dan Hammerstrom and Dan Lulich, The Proceedings of the IEEE, Vol. 84, No. 7, July 1996, pp. 1005
  9. "A Digital VLSI Architecture for Neural Network Emulation, Pattern Recognition, and Image Processing," Dan Hammerstrom, Naval Research News, Office of Naval Research, Three/1995 Vol. XLVII, pp. 27-43.
  10. "An 11 Million Transistor Digital Neural Network Execution Engine", IEEE International Solid-State Circuits Conference, 1991, M. Griffin, G. Tahara, K. Knorpp, R. Pinkham, B. Riley, D. Hammerstrom, and E. Means, pp. 180-181.