C-BRIC Researchers at Arizona State to Present at IEDM

C-BRIC researchers Zhenyu Wang, Gopikrishnan Raveendran Nair, Gokul Krishnan, Jae-sun Seo, and Yu (Kevin) Cao of Arizona State University and Vijay Narayanan will present at the 68th Annual International Electron Devices Meeting (IEDM) to run from December 3-7, 2022. IEDM is sponsored by IEEE. It is the “preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling.”

 

The ASU team and their collaborators Ninoo Cherian and Chaitali Chakrabarti also from Arizona State and Sumit K. Mandal and Umit Y. Ogras of the University of Wisconsin, Madison will present "AI Computing in Light of 2.5D Interconnect Roadmap: Big-Little Chiplets for In-memory Acceleration" at the conference. The paper focuses on a pathfinding study to bridge AI algorithms with the chiplet architecture, covering in-memory computing (IMC), network-on-package (NoP), and heterogeneous architecture. Using their newly developed benchmarking tool, SIAM, the group worked to perform simulations on representative algorithms (DNNs, transformers and GCNs). They discovered a roadmap of 2.5D interconnect for technological exploration; a generic mapping and optimization methodology that reveals various bandwidth needs in AI computing, where the evolution of 2.5D interconnect can or cannot support; and a big-little chiplet architecture that matches the non-uniform nature of AI algorithms. Overall, heterogeneous big-little chiplets with 2.5D interconnect advance AI computing to the next level of data movement and computing efficiency.

 

Narayanan along with collaborators Yi Xiao and Yixin Xu also of Penn State, Zhouhang Jiang, Shan Deng, Zijian Zhao, and Kai Ni of Rochester Institute of Technology, Antik Mallick and Nikhil Shukla of the University of Virginia, Limeng Sun and Xueqing Li of Tsinghua University, and Rajiv V. Joshi of IBM will present “On the Write Schemes and Efficiency of FeFET 1T NOR Array for Embedded Nonvolatile Memory and Beyond.” In this work, they demonstrate a comprehensive model which reflects two FeFET write mechanisms, three write schemes for conventional FeFET 1T NOR arrays and another one for the diagonal array, a study of parasitic parameters, and an implementation of FeFET 1T NOR array in the Ising machine system.