Project Name: αCassiopeiae 8800
Project Functional Description:
We plan to create a miniaturized version of the Altair 8800, one of the first personal microcomputers. Our system is implemented as 4 different PCBs, which are comprised of 3 unique PCB designs.
- The design is comprised of a Front Panel PCB, a backplane PCB, and a multi-function card PCB.
- A 44-pin bus interface provides 16-address lines, 8 data lines, and 20 bus control lines. The bus implementation is driven by the Programmable I/O (PIO) feature of Raspberry Pi microcontrollers, which allows for the configuration of state machines to allow for custom serial and parallel I/O.
- Delivery of bus signals and 3.3V power is facilitated by the backplane PCB. The backplane PCB connects to each card PCB via a DDR4 DIMM connector, and to the front panel PCB via a series of flat flex connectors.
- The user should be able to add optional expansion cards to allow more advanced functionality, for example, communication over UART. These additional cards interface with the same bus interface as the other cards do. The user should be able to add/remove these optional cards to achieve the functionality they desire. For our project, as a stretch goal, we plan on providing a working UART card with custom firmware, using the same PCB design as our CPU and RAM cards.
- Our machine will be powered via a USB-C 5V/3A rated power supply. The USB-C connector connects to a receptacle on the backplane board, which regulates it down to the 3.3V level required for our system.
- All components are mounted on a two-piece alumiunum extruded enclosure, with the front panel mounted with machine screws on the front, the backplane riding on the mounting "ribs" within the alumiunum shell, each card mounted on the DIMM receptacles of the backplane, and two separate mechanical-only rear plates mounted with machine screws on the back of the device, separate as to allow for the two parts of the enclosure to slide apart even after assembly, with the removal to the top two front panel machine screws.
Components
Front Panel
The front panel will make up the user interface of our design. It will use an array of reverse mounted SMT LEDs (such as the KingBright AA3528SECKT) to display information to the user, of which consists of 16 address bit lights, 8 data bit lights, and up to 8 different status lights.
The front panel is implemented using an RP2350B, making use of an ABM8-272-T3 external crystal oscialltor, and W25Q128JVS 128MB external flash.
As a user interface, the front panel will provide various slide switches for CPU control, memory examination, and reset functions. For the toggle dual-throw interface on the original Altair 8800, these will be implemented using slide switches. Whereas, the momentary dual-throw switches will be each implemented using two (2) tactile button switches.
The address and data LEDs can either be driven off of the bus directly, or via the microcontroller (to reflect the current state of each slide switch), which is chosen via a selection chip (based on the device's examine, single-step state).
The clock generation will also be on the front panel, and will use switches/buttons to allow normal clock operation (2 MHz) and support single-step clock (asserting the single-step signal in this mode). In order to assert address control, the front panel must begin a routine, where it asserts an interrupt, and drives the data lines to form a JMP instruction on-the-fly.
This board is intended to be mounted externally, meaning that the solder mask and silkscreen will be exposed at the front of the device. The front panel features a layout and silkscreen design that is reminiscent of the original Altair 8800's front panel to a reasonable level of aesthetic fidelity.
The board connects to the backplane via a series of flat flex connectors.
LEDs and Switches Detail
| LEDs | | | Switches | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Group | Sub-Group | Label | Description | | | Group | Sub-Group | Sub-Group | Type | Label | Description |
| Status | INTE | Bus PINTE | | | Power | Toggle | ON/OFF | ||||
| Status | PROT | Bus PROT | | | Data/Address | 6th Address Octal | 3rd Sense Octal | Toggle | 15 | ||
| Status | Silkscreen | MEMR | Bus SMEMR | | | Data/Address | 5th Address Octal | 3rd Sense Octal | Toggle | 14 | |
| Status | Silkscreen | INP | Bus SINP | | | Data/Address | 5th Address Octal | 2nd Sense Octal | Toggle | 13 | |
| Status | Silkscreen | M1 | Bus SM1 | | | Data/Address | 5th Address Octal | 2nd Sense Octal | Toggle | 12 | |
| Status | Silkscreen | OUT | Bus SOUT | | | Data/Address | 4th Address Octal | 2nd Sense Octal | Toggle | 11 | |
| Status | Silkscreen | HLTA | Bus SHLTA | | | Data/Address | 4th Address Octal | 1st Sense Octal | Toggle | 10 | |
| Status | Silkscreen | STACK | Bus SSTACK | | | Data/Address | 4th Address Octal | 1st Sense Octal | Toggle | 9 | |
| Status | Silkscreen | WO | Bus SWO | | | Data/Address | 3rd Address Octal | 1st Sense Octal | Toggle | 8 | |
| Status | Silkscreen | INT | Bus SINTA | | | Data/Address | 3rd Address Octal | 3rd Data Octal | Toggle | 7 | |
| Run State | WAIT | Bus PWAIT | | | Data/Address | 3rd Address Octal | 3rd Data Octal | Toggle | 6 | ||
| Run State | HLDA | Bus XRDY | | | Data/Address | 2nd Address Octal | 2nd Data Octal | Toggle | 5 | ||
| Address | 6th Octal | A15 | Bus A15 | | | Data/Address | 2nd Address Octal | 2nd Data Octal | Toggle | 4 | |
| Address | 5th Octal | A14 | Bus A14 | | | Data/Address | 2nd Address Octal | 2nd Data Octal | Toggle | 3 | |
| Address | 5th Octal | A13 | Bus A13 | | | Data/Address | 1st Address Octal | 1st Data Octal | Toggle | 2 | |
| Address | 5th Octal | A12 | Bus A12 | | | Data/Address | 1st Address Octal | 1st Data Octal | Toggle | 1 | |
| Address | 4th Octal | A11 | Bus A11 | | | Data/Address | 1st Address Octal | 1st Data Octal | Toggle | 0 | |
| Address | 4th Octal | A10 | Bus A10 | | | Control | Run State | Momentary | STOP | ||
| Address | 4th Octal | A9 | Bus A9 | | | Control | Run State | Momentary | RUN | ||
| Address | 3rd Octal | A8 | Bus A8 | | | Control | Run State | Momentary | SINGLE STEP | ||
| Address | 3rd Octal | A7 | Bus A7 | | | Control | Examine | Momentary | EXAMINE | ||
| Address | 3rd Octal | A6 | Bus A6 | | | Control | Examine | Momentary | EXAMINE NEXT | ||
| Address | 2nd Octal | A5 | Bus A5 | | | Control | Deposit | Momentary | DEPOSIT | ||
| Address | 2nd Octal | A4 | Bus A4 | | | Control | Deposit | Momentary | DEPOSIT NEXT | ||
| Address | 2nd Octal | A3 | Bus A3 | | | Control | Run State | Momentary | RESET | ||
| Address | 1st Octal | A2 | Bus A2 | | | Control | Run State | Momentary | CLR | ||
| Address | 1st Octal | A1 | Bus A1 | | | Control | Protection | Momentary | PROTECT | ||
| Address | 1st Octal | A0 | Bus A0 | | | Control | Protection | Momentary | UNPROTECT | ||
| Data | 3rd Octal | D7 | Bus D7 | | | Control | Auxiliary | Momentary | AUX1 | ||
| Data | 3rd Octal | D6 | Bus D6 | | | Control | Auxiliary | Momentary | AUX2 | ||
| Data | 2nd Octal | D5 | Bus D5 | | | ||||||
| Data | 2nd Octal | D4 | Bus D4 | | | ||||||
| Data | 2nd Octal | D3 | Bus D3 | | | ||||||
| Data | 1st Octal | D2 | Bus D2 | | | ||||||
| Data | 1st Octal | D1 | Bus D1 | | | ||||||
| Data | 1st Octal | D0 | Bus D0 | | | ||||||
Internal Cards
For this project, the PCB design for the CPU, RAM, and UART cards is identical, and the functionality is differentiated on the matter of the firmware loaded, the state of various jumpers on the PCB (to allow for the changing of I/O circuits), and the population of certain components (such as I/O expanders, UART connectors, etc.). Each board integrates the RP2350B microcontroller (with an external ABM8-272-T3 crystal oscillator and W25Q128JVS 128MB external flash). Each board features an internal USB-C connector, allowing for the board to be optionally self-powered during UF2 programming scenarios. Each board also features an SWD connector to allow for external programming. Bus and power signals are broken out into a DDR4 DIMM edge connector, which interfaces with the DDR4 DIMM receptacle on the backplane PCB. Based on the firmware implementation, the device can emulate either an the Intel 8080 processor OR providing at least 4 KB of addressable memory for program execution (for example for use with 4K BASIC) OR a UART device that responds to I/O bus operations, and tranceives them to an external UART port.
Backplane PCB
The backplane PCB is mounted internally to the enclosure, and features as least 3 DDR4 DIMM
receptacles.
The PCB provides a regulated power supply, which includes a 5V to 3.3V step-down power supply
using a reference buck converter design. 5V/3A power is provided externally via a USB-C
connector mounted on the backplane board. This ensures stable voltage levels for all onboard
components, preventing overvoltage damage while maintaining efficient power delivery to the CPU,
memory, front panel, and any expansion cards. The backplane facilitates power delivery to the
CPU and RAM cards via DDR4 DIMMs, and to the front panel via a series of FFC connectors. The
board is laid out in such a way that there is even power/voltage distribution throughout the
board.
Bus specification
| Line | Usage | Pincount |
|---|---|---|
| ~CLOCK | bus clock | 1 |
| A0-A15 | Address (CPU driven) | 16 |
| A0-D7 | Data (tri-state) | 8 |
| PINTE | interrupt enable | 1 |
| PROT | memory protection | 1 |
| SMEMR | memory read strobe | 1 |
| SINP | input IO cycle | 1 |
| SM1 | first machine cycle of instruction flag | 1 |
| SOUT | ouput IO cycle | 1 |
| SHLTA | halt | 1 |
| SSTACK | stack operation | 1 |
| SWO | write-out | 1 |
| SINTA | interrupt acknowledge | 1 |
| XRDY | memory ready | 1 |
| PWAIT | mem/IO wait | 1 |
| PRDY | IO ready | 1 |
| ~PINT | interrupt request | 1 |
| ~PRESET | reset | 1 |
| ~PHOLD | "hold" bus control | 1 |
| PDBIN | data bus in | 1 |
| MWRT | memory write strobe | 1 |
| PANEL | front panel data control | 1 |
Diagram
Project Specific Design Requirements (PSDRs):
- (Hardware) Ability to support communication between CPU and RAM cards over a simplified S-100 inspired bus, using a backplane PCB with DDR4 DIMM edge connectors to connect bus signals between cards.
- (Hardware) An ability to interface the RP2350B microcontroller with I2C-based MCP23017 and MCP23008 I/O expanders to reduce GPIO pin usage, allowing support of all 44 bus signals and some extras that are necessary.
- (Hardware) An ability to provide a regulated power supply is fulfilled by the backplane board, which includes a 5V to 3.3V step-down power supply using a reference buck converter design.
- (Software) An ability to emulate the Intel 8080 processor in software, written in Rust to decode and execute Intel 8080 instructions with accurate cycle timing and interrupt management. This emulator will be designed to emulate 8080 machine cycles, which respect concepts such as waiting for I/O operations.
- (Software) Ability to manage parallel bus data exchange using Programmable IO (PIO) assembler routines, which are assembled and processed by the CPU, RAM, and front panel software. These routines must allow for multi-device control of the same data lines on the bus.
- (Stretch, Hardware) An ability for a UART card to implement the UART protocol, using I/O control lines (separate from memory control lines), and tranceive the information to an external UART port.